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llvm-mirror/test/CodeGen/ARM/pr18364-movw.ll
David Blaikie ab043ff680 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794
2015-02-27 21:17:42 +00:00

35 lines
841 B
LLVM

; RUN: llc < %s -mtriple=armv5te | FileCheck %s --check-prefix=V5
; RUN: llc < %s -mtriple=armv6 | FileCheck %s --check-prefix=V6
; RUN: llc < %s -mtriple=armv6t2 | FileCheck %s --check-prefix=V6T2
; RUN: llc < %s -mtriple=armv7 | FileCheck %s --check-prefix=V7
; PR18364
define i64 @f() #0 {
entry:
; V5-NOT: movw
; V6-NOT: movw
; V6T2: movw
; V7: movw
%y = alloca i64, align 8
%z = alloca i64, align 8
store i64 1, i64* %y, align 8
store i64 11579764786944, i64* %z, align 8
%0 = load i64, i64* %y, align 8
%1 = load i64, i64* %z, align 8
%sub = sub i64 %0, %1
ret i64 %sub
}
define i64 @g(i64 %a, i32 %b) #0 {
entry:
; V5-NOT: movw
; V6-NOT: movw
; V6T2: movw
; V7: movw
%0 = mul i64 %a, 86400000
%mul = add i64 %0, -210866803200000
%conv = sext i32 %b to i64
%add = add nsw i64 %mul, %conv
ret i64 %add
}