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https://github.com/RPCS3/llvm-mirror.git
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b497a0eb34
return StringSwitch<int>(Flags)
.Case("g", 0x1)
.Case("nzcvq", 0x2)
.Case("nzcvqg", 0x3)
.Default(-1);
...
// The _g and _nzcvqg versions are only valid if the DSP extension is
// available.
if (!Subtarget->hasThumb2DSP() && (Mask & 0x2))
return -1;
ARMARM confirms that the comment is right, and the code was wrong.
llvm-svn: 244029
144 lines
5.0 KiB
LLVM
144 lines
5.0 KiB
LLVM
; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=MCORE
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; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m3 2>&1 | FileCheck %s --check-prefix=M3CORE
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; RUN: not llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE
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; ACORE: LLVM ERROR: Invalid register name "control".
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; M3CORE: LLVM ERROR: Invalid register name "xpsr_nzcvqg".
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define i32 @read_mclass_registers() nounwind {
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entry:
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; MCORE-LABEL: read_mclass_registers:
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; MCORE: mrs r0, apsr
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; MCORE: mrs r1, iapsr
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; MCORE: mrs r1, eapsr
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; MCORE: mrs r1, xpsr
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; MCORE: mrs r1, ipsr
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; MCORE: mrs r1, epsr
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; MCORE: mrs r1, iepsr
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; MCORE: mrs r1, msp
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; MCORE: mrs r1, psp
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; MCORE: mrs r1, primask
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; MCORE: mrs r1, basepri
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; MCORE: mrs r1, basepri_max
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; MCORE: mrs r1, faultmask
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; MCORE: mrs r1, control
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%0 = call i32 @llvm.read_register.i32(metadata !0)
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%1 = call i32 @llvm.read_register.i32(metadata !4)
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%add1 = add i32 %1, %0
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%2 = call i32 @llvm.read_register.i32(metadata !8)
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%add2 = add i32 %add1, %2
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%3 = call i32 @llvm.read_register.i32(metadata !12)
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%add3 = add i32 %add2, %3
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%4 = call i32 @llvm.read_register.i32(metadata !16)
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%add4 = add i32 %add3, %4
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%5 = call i32 @llvm.read_register.i32(metadata !17)
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%add5 = add i32 %add4, %5
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%6 = call i32 @llvm.read_register.i32(metadata !18)
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%add6 = add i32 %add5, %6
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%7 = call i32 @llvm.read_register.i32(metadata !19)
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%add7 = add i32 %add6, %7
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%8 = call i32 @llvm.read_register.i32(metadata !20)
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%add8 = add i32 %add7, %8
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%9 = call i32 @llvm.read_register.i32(metadata !21)
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%add9 = add i32 %add8, %9
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%10 = call i32 @llvm.read_register.i32(metadata !22)
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%add10 = add i32 %add9, %10
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%11 = call i32 @llvm.read_register.i32(metadata !23)
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%add11 = add i32 %add10, %11
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%12 = call i32 @llvm.read_register.i32(metadata !24)
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%add12 = add i32 %add11, %12
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%13 = call i32 @llvm.read_register.i32(metadata !25)
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%add13 = add i32 %add12, %13
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ret i32 %add13
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}
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define void @write_mclass_registers(i32 %x) nounwind {
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entry:
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; MCORE-LABEL: write_mclass_registers:
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; MCORE: msr apsr_nzcvqg, r0
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; MCORE: msr apsr_nzcvq, r0
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; MCORE: msr apsr_g, r0
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; MCORE: msr apsr_nzcvqg, r0
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; MCORE: msr iapsr_nzcvqg, r0
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; MCORE: msr iapsr_nzcvq, r0
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; MCORE: msr iapsr_g, r0
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; MCORE: msr iapsr_nzcvqg, r0
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; MCORE: msr eapsr_nzcvqg, r0
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; MCORE: msr eapsr_nzcvq, r0
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; MCORE: msr eapsr_g, r0
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; MCORE: msr eapsr_nzcvqg, r0
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; MCORE: msr xpsr_nzcvqg, r0
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; MCORE: msr xpsr_nzcvq, r0
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; MCORE: msr xpsr_g, r0
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; MCORE: msr xpsr_nzcvqg, r0
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; MCORE: msr ipsr, r0
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; MCORE: msr epsr, r0
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; MCORE: msr iepsr, r0
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; MCORE: msr msp, r0
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; MCORE: msr psp, r0
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; MCORE: msr primask, r0
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; MCORE: msr basepri, r0
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; MCORE: msr basepri_max, r0
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; MCORE: msr faultmask, r0
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; MCORE: msr control, r0
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call void @llvm.write_register.i32(metadata !0, i32 %x)
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call void @llvm.write_register.i32(metadata !1, i32 %x)
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call void @llvm.write_register.i32(metadata !2, i32 %x)
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call void @llvm.write_register.i32(metadata !3, i32 %x)
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call void @llvm.write_register.i32(metadata !4, i32 %x)
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call void @llvm.write_register.i32(metadata !5, i32 %x)
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call void @llvm.write_register.i32(metadata !6, i32 %x)
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call void @llvm.write_register.i32(metadata !7, i32 %x)
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call void @llvm.write_register.i32(metadata !8, i32 %x)
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call void @llvm.write_register.i32(metadata !9, i32 %x)
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call void @llvm.write_register.i32(metadata !10, i32 %x)
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call void @llvm.write_register.i32(metadata !11, i32 %x)
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call void @llvm.write_register.i32(metadata !12, i32 %x)
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call void @llvm.write_register.i32(metadata !13, i32 %x)
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call void @llvm.write_register.i32(metadata !14, i32 %x)
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call void @llvm.write_register.i32(metadata !15, i32 %x)
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call void @llvm.write_register.i32(metadata !16, i32 %x)
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call void @llvm.write_register.i32(metadata !17, i32 %x)
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call void @llvm.write_register.i32(metadata !18, i32 %x)
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call void @llvm.write_register.i32(metadata !19, i32 %x)
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call void @llvm.write_register.i32(metadata !20, i32 %x)
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call void @llvm.write_register.i32(metadata !21, i32 %x)
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call void @llvm.write_register.i32(metadata !22, i32 %x)
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call void @llvm.write_register.i32(metadata !23, i32 %x)
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call void @llvm.write_register.i32(metadata !24, i32 %x)
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call void @llvm.write_register.i32(metadata !25, i32 %x)
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ret void
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}
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declare i32 @llvm.read_register.i32(metadata) nounwind
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declare void @llvm.write_register.i32(metadata, i32) nounwind
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!0 = !{!"apsr"}
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!1 = !{!"apsr_nzcvq"}
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!2 = !{!"apsr_g"}
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!3 = !{!"apsr_nzcvqg"}
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!4 = !{!"iapsr"}
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!5 = !{!"iapsr_nzcvq"}
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!6 = !{!"iapsr_g"}
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!7 = !{!"iapsr_nzcvqg"}
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!8 = !{!"eapsr"}
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!9 = !{!"eapsr_nzcvq"}
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!10 = !{!"eapsr_g"}
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!11 = !{!"eapsr_nzcvqg"}
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!12 = !{!"xpsr"}
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!13 = !{!"xpsr_nzcvq"}
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!14 = !{!"xpsr_g"}
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!15 = !{!"xpsr_nzcvqg"}
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!16 = !{!"ipsr"}
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!17 = !{!"epsr"}
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!18 = !{!"iepsr"}
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!19 = !{!"msp"}
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!20 = !{!"psp"}
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!21 = !{!"primask"}
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!22 = !{!"basepri"}
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!23 = !{!"basepri_max"}
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!24 = !{!"faultmask"}
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!25 = !{!"control"}
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