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306d4457fd
Created a Thumb2 predicated pattern matcher that uses Thumb2 and
HasT2ExtractPack and used it to redefine the patterns for sxta{b|h}
and uxta{b|h}. Also used the similar patterns to fill in isel pattern
gaps for the corresponding instructions in the ARM backend.
The patch is mainly changes to tests since most of this functionality
appears not to have been tested.
Differential Revision: https://reviews.llvm.org/D23273
llvm-svn: 278207
114 lines
2.5 KiB
LLVM
114 lines
2.5 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s --check-prefix=CHECK-V6
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; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s --check-prefix=CHECK-V7
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define i32 @test0(i8 %A) {
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; CHECK-LABEL: test0
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; CHECK-V6: sxtb r0, r0
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; CHECK-V7: sxtb r0, r0
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%B = sext i8 %A to i32
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ret i32 %B
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}
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define signext i8 @test1(i32 %A) {
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; CHECK-LABEL: test1
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; CHECK-V6: lsr r0, r0, #8
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; CHECK-V6: sxtb r0, r0
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; CHECK-V6-NOT: sbfx
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; CHECk-V7: sbfx r0, r0, #8, #8
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%B = lshr i32 %A, 8
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%C = shl i32 %A, 24
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%D = or i32 %B, %C
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%E = trunc i32 %D to i8
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ret i8 %E
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}
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define signext i32 @test2(i32 %A, i32 %X) {
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; CHECK-LABEL: test2
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; CHECK-V6: sxtab r0, r1, r0, ror #8
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; CHECK-V7: sxtab r0, r1, r0, ror #8
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%B = lshr i32 %A, 8
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%C = shl i32 %A, 24
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%D = or i32 %B, %C
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%E = trunc i32 %D to i8
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%F = sext i8 %E to i32
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%G = add i32 %F, %X
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ret i32 %G
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}
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define signext i32 @test3(i32 %A, i32 %X) {
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; CHECK-LABEL: test3
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; CHECK-V6: sxtab r0, r1, r0, ror #16
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; CHECK-V7: sxtab r0, r1, r0, ror #16
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%B = lshr i32 %A, 16
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%C = shl i32 %A, 16
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%D = or i32 %B, %C
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%E = trunc i32 %D to i8
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%F = sext i8 %E to i32
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%G = add i32 %F, %X
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ret i32 %G
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}
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define signext i32 @test4(i32 %A, i32 %X) {
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; CHECK-LABEL: test4
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; CHECK-V6: sxtah r0, r1, r0, ror #8
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; CHECK-V7: sxtah r0, r1, r0, ror #8
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%B = lshr i32 %A, 8
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%C = shl i32 %A, 24
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%D = or i32 %B, %C
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%E = trunc i32 %D to i16
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%F = sext i16 %E to i32
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%G = add i32 %F, %X
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ret i32 %G
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}
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define signext i32 @test5(i32 %A, i32 %X) {
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; CHECK-LABEL: test5
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; CHECK-V6: sxtah r0, r1, r0, ror #24
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; CHECK-V7: sxtah r0, r1, r0, ror #24
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%B = lshr i32 %A, 24
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%C = shl i32 %A, 8
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%D = or i32 %B, %C
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%E = trunc i32 %D to i16
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%F = sext i16 %E to i32
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%G = add i32 %F, %X
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ret i32 %G
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}
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define i32 @test6(i8 %A, i32 %X) {
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; CHECK-LABEL: test6
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; CHECK-V6: sxtab r0, r1, r0
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; CHECK-V7: sxtab r0, r1, r0
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%sext = sext i8 %A to i32
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%add = add i32 %X, %sext
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ret i32 %add
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}
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define i32 @test7(i32 %A, i32 %X) {
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; CHECK-LABEL: test7
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; CHECK-V6: sxtab r0, r1, r0
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; CHECK-V7: sxtab r0, r1, r0
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%shl = shl i32 %A, 24
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%shr = ashr i32 %shl, 24
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%add = add i32 %X, %shr
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ret i32 %add
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}
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define i32 @test8(i16 %A, i32 %X) {
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; CHECK-LABEL: test8
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; CHECK-V6: sxtah r0, r1, r0
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; CHECK-V7: sxtah r0, r1, r0
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%sext = sext i16 %A to i32
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%add = add i32 %X, %sext
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ret i32 %add
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}
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define i32 @test9(i32 %A, i32 %X) {
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; CHECK-LABEL: test9
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; CHECK-V6: sxtah r0, r1, r0
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; CHECK-V7: sxtah r0, r1, r0
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%shl = shl i32 %A, 16
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%shr = ashr i32 %shl, 16
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%add = add i32 %X, %shr
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ret i32 %add
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}
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