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7d64810efd
The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. llvm-svn: 306514
70 lines
1.8 KiB
LLVM
70 lines
1.8 KiB
LLVM
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
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; RUN: llc -mtriple=armeb-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
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define i64 @f0(i64 %A, i64 %B) {
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; CHECK-LABEL: f0:
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; CHECK-LE: lsrs r3, r3, #1
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; CHECK-LE-NEXT: rrx r2, r2
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; CHECK-LE-NEXT: subs r0, r0, r2
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; CHECK-LE-NEXT: sbc r1, r1, r3
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; CHECK-BE: lsrs r2, r2, #1
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; CHECK-BE-NEXT: rrx r3, r3
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; CHECK-BE-NEXT: subs r1, r1, r3
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; CHECK-BE-NEXT: sbc r0, r0, r2
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%tmp = bitcast i64 %A to i64
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%tmp2 = lshr i64 %B, 1
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%tmp3 = sub i64 %tmp, %tmp2
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ret i64 %tmp3
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}
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define i32 @f1(i64 %x, i64 %y) {
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; CHECK-LABEL: f1:
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; CHECK-LE: lsl{{.*}}r2
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; CHECK-BE: lsl{{.*}}r3
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%a = shl i64 %x, %y
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%b = trunc i64 %a to i32
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ret i32 %b
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}
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define i32 @f2(i64 %x, i64 %y) {
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; CHECK-LABEL: f2:
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; CHECK-LE: rsb r3, r2, #32
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; CHECK-LE-NEXT: lsr{{.*}}r2
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; CHECK-LE-NEXT: sub r2, r2, #32
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; CHECK-LE-NEXT: orr r0, r0, r1, lsl r3
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; CHECK-LE-NEXT: cmp r2, #0
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; CHECK-LE-NEXT: asrge r0, r1, r2
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; CHECK-BE: rsb r2, r3, #32
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; CHECK-BE-NEXT: lsr{{.*}}r3
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; CHECK-BE-NEXT: orr r1, r1, r0, lsl r2
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; CHECK-BE-NEXT: sub r2, r3, #32
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; CHECK-BE-NEXT: cmp r2, #0
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; CHECK-BE-NEXT: asrge r1, r0, r2
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%a = ashr i64 %x, %y
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%b = trunc i64 %a to i32
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ret i32 %b
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}
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define i32 @f3(i64 %x, i64 %y) {
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; CHECK-LABEL: f3:
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; CHECK-LE: rsb r3, r2, #32
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; CHECK-LE-NEXT: lsr{{.*}}r2
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; CHECK-LE-NEXT: sub r2, r2, #32
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; CHECK-LE-NEXT: orr r0, r0, r1, lsl r3
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; CHECK-LE-NEXT: cmp r2, #0
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; CHECK-LE-NEXT: lsrge r0, r1, r2
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; CHECK-BE: rsb r2, r3, #32
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; CHECK-BE-NEXT: lsr{{.*}}r3
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; CHECK-BE-NEXT: orr r1, r1, r0, lsl r2
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; CHECK-BE-NEXT: sub r2, r3, #32
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; CHECK-BE-NEXT: cmp r2, #0
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; CHECK-BE-NEXT: lsrge r1, r0, r2
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%a = lshr i64 %x, %y
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%b = trunc i64 %a to i32
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ret i32 %b
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}
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