mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-23 04:52:54 +02:00
62ad0a5cf3
As noted in the D44909 review, the transform from (fptosi+sitofp) to ftrunc
can produce -0.0 where the original code does not:
#include <stdio.h>
int main(int argc) {
float x;
x = -0.8 * argc;
printf("%f\n", (float)((int)x));
return 0;
}
$ clang -O0 -mavx fp.c ; ./a.out
0.000000
$ clang -O1 -mavx fp.c ; ./a.out
-0.000000
Ideally, we'd use IR/node flags to predicate the transform, but the IR parser
doesn't currently allow fast-math-flags on the cast instructions. So for now,
just use the function attribute that corresponds to clang's "-fno-signed-zeros"
option.
Differential Revision: https://reviews.llvm.org/D48085
llvm-svn: 335761
59 lines
2.3 KiB
LLVM
59 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc < %s -mtriple=x86_64-- -mattr=avx | FileCheck %s --check-prefixes=AVX,AVX1
|
|
; RUN: llc < %s -mtriple=x86_64-- -mattr=avx512f,avx512vl | FileCheck %s --check-prefixes=AVX,AVX512
|
|
|
|
; PR37751 - https://bugs.llvm.org/show_bug.cgi?id=37751
|
|
; We can't combine into 'round' instructions because the behavior is different for out-of-range values.
|
|
|
|
declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>)
|
|
declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>)
|
|
|
|
define <8 x float> @float_to_int_to_float_mem_v8f32(<8 x float>* %p) #0 {
|
|
; AVX-LABEL: float_to_int_to_float_mem_v8f32:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vcvttps2dq (%rdi), %ymm0
|
|
; AVX-NEXT: vcvtdq2ps %ymm0, %ymm0
|
|
; AVX-NEXT: retq
|
|
%x = load <8 x float>, <8 x float>* %p, align 16
|
|
%fptosi = tail call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %x)
|
|
%sitofp = sitofp <8 x i32> %fptosi to <8 x float>
|
|
ret <8 x float> %sitofp
|
|
}
|
|
|
|
define <8 x float> @float_to_int_to_float_reg_v8f32(<8 x float> %x) #0 {
|
|
; AVX-LABEL: float_to_int_to_float_reg_v8f32:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vcvttps2dq %ymm0, %ymm0
|
|
; AVX-NEXT: vcvtdq2ps %ymm0, %ymm0
|
|
; AVX-NEXT: retq
|
|
%fptosi = tail call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %x)
|
|
%sitofp = sitofp <8 x i32> %fptosi to <8 x float>
|
|
ret <8 x float> %sitofp
|
|
}
|
|
|
|
define <4 x double> @float_to_int_to_float_mem_v4f64(<4 x double>* %p) #0 {
|
|
; AVX-LABEL: float_to_int_to_float_mem_v4f64:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vcvttpd2dqy (%rdi), %xmm0
|
|
; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
|
|
; AVX-NEXT: retq
|
|
%x = load <4 x double>, <4 x double>* %p, align 16
|
|
%fptosi = tail call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %x)
|
|
%sitofp = sitofp <4 x i32> %fptosi to <4 x double>
|
|
ret <4 x double> %sitofp
|
|
}
|
|
|
|
define <4 x double> @float_to_int_to_float_reg_v4f64(<4 x double> %x) #0 {
|
|
; AVX-LABEL: float_to_int_to_float_reg_v4f64:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vcvttpd2dq %ymm0, %xmm0
|
|
; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
|
|
; AVX-NEXT: retq
|
|
%fptosi = tail call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %x)
|
|
%sitofp = sitofp <4 x i32> %fptosi to <4 x double>
|
|
ret <4 x double> %sitofp
|
|
}
|
|
|
|
attributes #0 = { "no-signed-zeros-fp-math"="true" }
|
|
|