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29abad3787
a zero register. Previously I tried this and saw LLVM unable to transform this to fold with memory operands such as spill slot rematerialization. However, it clearly works as shown in this patch. We turn these into `cmpb $0, <mem>` when useful for folding a memory operand without issue. This form has no disadvantage compared to `testb $-1, <mem>`. So overall, this is likely no worse and may be slightly smaller in some cases due to the `testb %reg, %reg` form. Differential Revision: https://reviews.llvm.org/D45475 llvm-svn: 330269
280 lines
10 KiB
LLVM
280 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=i386-linux-gnu -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=32-ALL,32-GOOD-RA
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; RUN: llc -mtriple=i386-linux-gnu -verify-machineinstrs -pre-RA-sched=fast %s -o - | FileCheck %s --check-prefixes=32-ALL,32-FAST-RA
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; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=64-ALL,64-GOOD-RA
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; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs -pre-RA-sched=fast %s -o - | FileCheck %s --check-prefixes=64-ALL,64-FAST-RA
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; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs -mattr=+sahf %s -o - | FileCheck %s --check-prefixes=64-ALL,64-GOOD-RA-SAHF
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; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs -mattr=+sahf -pre-RA-sched=fast %s -o - | FileCheck %s --check-prefixes=64-ALL,64-FAST-RA-SAHF
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; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs -mcpu=corei7 %s -o - | FileCheck %s --check-prefixes=64-ALL,64-GOOD-RA-SAHF
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declare i32 @foo()
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declare i32 @bar(i64)
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; In the following case when using fast scheduling we get a long chain of
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; EFLAGS save/restore due to a sequence of:
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; cmpxchg8b (implicit-def eflags)
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; eax = copy eflags
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; adjcallstackdown32
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; ...
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; use of eax
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; During PEI the adjcallstackdown32 is replaced with the subl which
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; clobbers eflags, effectively interfering in the liveness interval. However,
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; we then promote these copies into independent conditions in GPRs that avoids
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; repeated saving and restoring logic and can be trivially managed by the
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; register allocator.
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define i64 @test_intervening_call(i64* %foo, i64 %bar, i64 %baz) nounwind {
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; 32-GOOD-RA-LABEL: test_intervening_call:
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; 32-GOOD-RA: # %bb.0: # %entry
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; 32-GOOD-RA-NEXT: pushl %ebx
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; 32-GOOD-RA-NEXT: pushl %esi
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; 32-GOOD-RA-NEXT: pushl %eax
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; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %eax
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; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %edx
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; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %ebx
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; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %esi
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; 32-GOOD-RA-NEXT: lock cmpxchg8b (%esi)
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; 32-GOOD-RA-NEXT: setne %bl
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; 32-GOOD-RA-NEXT: subl $8, %esp
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; 32-GOOD-RA-NEXT: pushl %edx
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; 32-GOOD-RA-NEXT: pushl %eax
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; 32-GOOD-RA-NEXT: calll bar
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; 32-GOOD-RA-NEXT: addl $16, %esp
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; 32-GOOD-RA-NEXT: testb %bl, %bl
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; 32-GOOD-RA-NEXT: jne .LBB0_3
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; 32-GOOD-RA-NEXT: # %bb.1: # %t
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; 32-GOOD-RA-NEXT: movl $42, %eax
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; 32-GOOD-RA-NEXT: jmp .LBB0_2
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; 32-GOOD-RA-NEXT: .LBB0_3: # %f
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; 32-GOOD-RA-NEXT: xorl %eax, %eax
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; 32-GOOD-RA-NEXT: .LBB0_2: # %t
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; 32-GOOD-RA-NEXT: xorl %edx, %edx
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; 32-GOOD-RA-NEXT: addl $4, %esp
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; 32-GOOD-RA-NEXT: popl %esi
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; 32-GOOD-RA-NEXT: popl %ebx
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; 32-GOOD-RA-NEXT: retl
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;
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; 32-FAST-RA-LABEL: test_intervening_call:
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; 32-FAST-RA: # %bb.0: # %entry
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; 32-FAST-RA-NEXT: pushl %ebx
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; 32-FAST-RA-NEXT: pushl %esi
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; 32-FAST-RA-NEXT: pushl %eax
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; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %esi
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; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %ebx
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; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %eax
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; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %edx
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; 32-FAST-RA-NEXT: lock cmpxchg8b (%esi)
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; 32-FAST-RA-NEXT: setne %bl
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; 32-FAST-RA-NEXT: subl $8, %esp
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; 32-FAST-RA-NEXT: pushl %edx
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; 32-FAST-RA-NEXT: pushl %eax
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; 32-FAST-RA-NEXT: calll bar
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; 32-FAST-RA-NEXT: addl $16, %esp
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; 32-FAST-RA-NEXT: testb %bl, %bl
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; 32-FAST-RA-NEXT: jne .LBB0_3
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; 32-FAST-RA-NEXT: # %bb.1: # %t
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; 32-FAST-RA-NEXT: movl $42, %eax
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; 32-FAST-RA-NEXT: jmp .LBB0_2
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; 32-FAST-RA-NEXT: .LBB0_3: # %f
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; 32-FAST-RA-NEXT: xorl %eax, %eax
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; 32-FAST-RA-NEXT: .LBB0_2: # %t
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; 32-FAST-RA-NEXT: xorl %edx, %edx
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; 32-FAST-RA-NEXT: addl $4, %esp
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; 32-FAST-RA-NEXT: popl %esi
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; 32-FAST-RA-NEXT: popl %ebx
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; 32-FAST-RA-NEXT: retl
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;
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; 64-ALL-LABEL: test_intervening_call:
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; 64-ALL: # %bb.0: # %entry
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; 64-ALL-NEXT: pushq %rbx
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; 64-ALL-NEXT: movq %rsi, %rax
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; 64-ALL-NEXT: lock cmpxchgq %rdx, (%rdi)
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; 64-ALL-NEXT: setne %bl
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; 64-ALL-NEXT: movq %rax, %rdi
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; 64-ALL-NEXT: callq bar
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; 64-ALL-NEXT: testb %bl, %bl
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; 64-ALL-NEXT: jne .LBB0_2
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; 64-ALL-NEXT: # %bb.1: # %t
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; 64-ALL-NEXT: movl $42, %eax
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; 64-ALL-NEXT: popq %rbx
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; 64-ALL-NEXT: retq
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; 64-ALL-NEXT: .LBB0_2: # %f
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; 64-ALL-NEXT: xorl %eax, %eax
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; 64-ALL-NEXT: popq %rbx
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; 64-ALL-NEXT: retq
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entry:
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%cx = cmpxchg i64* %foo, i64 %bar, i64 %baz seq_cst seq_cst
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%v = extractvalue { i64, i1 } %cx, 0
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%p = extractvalue { i64, i1 } %cx, 1
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call i32 @bar(i64 %v)
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br i1 %p, label %t, label %f
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t:
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ret i64 42
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f:
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ret i64 0
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}
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; Interesting in producing a clobber without any function calls.
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define i32 @test_control_flow(i32* %p, i32 %i, i32 %j) nounwind {
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; 32-ALL-LABEL: test_control_flow:
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; 32-ALL: # %bb.0: # %entry
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; 32-ALL-NEXT: movl {{[0-9]+}}(%esp), %eax
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; 32-ALL-NEXT: cmpl {{[0-9]+}}(%esp), %eax
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; 32-ALL-NEXT: jle .LBB1_6
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; 32-ALL-NEXT: # %bb.1: # %loop_start
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; 32-ALL-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; 32-ALL-NEXT: .p2align 4, 0x90
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; 32-ALL-NEXT: .LBB1_2: # %while.condthread-pre-split.i
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; 32-ALL-NEXT: # =>This Loop Header: Depth=1
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; 32-ALL-NEXT: # Child Loop BB1_3 Depth 2
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; 32-ALL-NEXT: movl (%ecx), %edx
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; 32-ALL-NEXT: .p2align 4, 0x90
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; 32-ALL-NEXT: .LBB1_3: # %while.cond.i
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; 32-ALL-NEXT: # Parent Loop BB1_2 Depth=1
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; 32-ALL-NEXT: # => This Inner Loop Header: Depth=2
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; 32-ALL-NEXT: movl %edx, %eax
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; 32-ALL-NEXT: xorl %edx, %edx
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; 32-ALL-NEXT: testl %eax, %eax
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; 32-ALL-NEXT: je .LBB1_3
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; 32-ALL-NEXT: # %bb.4: # %while.body.i
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; 32-ALL-NEXT: # in Loop: Header=BB1_2 Depth=1
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; 32-ALL-NEXT: lock cmpxchgl %eax, (%ecx)
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; 32-ALL-NEXT: jne .LBB1_2
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; 32-ALL-NEXT: # %bb.5:
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; 32-ALL-NEXT: xorl %eax, %eax
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; 32-ALL-NEXT: .LBB1_6: # %cond.end
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; 32-ALL-NEXT: retl
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;
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; 64-ALL-LABEL: test_control_flow:
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; 64-ALL: # %bb.0: # %entry
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; 64-ALL-NEXT: cmpl %edx, %esi
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; 64-ALL-NEXT: jle .LBB1_5
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; 64-ALL-NEXT: .p2align 4, 0x90
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; 64-ALL-NEXT: .LBB1_1: # %while.condthread-pre-split.i
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; 64-ALL-NEXT: # =>This Loop Header: Depth=1
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; 64-ALL-NEXT: # Child Loop BB1_2 Depth 2
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; 64-ALL-NEXT: movl (%rdi), %ecx
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; 64-ALL-NEXT: .p2align 4, 0x90
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; 64-ALL-NEXT: .LBB1_2: # %while.cond.i
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; 64-ALL-NEXT: # Parent Loop BB1_1 Depth=1
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; 64-ALL-NEXT: # => This Inner Loop Header: Depth=2
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; 64-ALL-NEXT: movl %ecx, %eax
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; 64-ALL-NEXT: xorl %ecx, %ecx
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; 64-ALL-NEXT: testl %eax, %eax
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; 64-ALL-NEXT: je .LBB1_2
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; 64-ALL-NEXT: # %bb.3: # %while.body.i
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; 64-ALL-NEXT: # in Loop: Header=BB1_1 Depth=1
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; 64-ALL-NEXT: lock cmpxchgl %eax, (%rdi)
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; 64-ALL-NEXT: jne .LBB1_1
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; 64-ALL-NEXT: # %bb.4:
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; 64-ALL-NEXT: xorl %esi, %esi
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; 64-ALL-NEXT: .LBB1_5: # %cond.end
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; 64-ALL-NEXT: movl %esi, %eax
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; 64-ALL-NEXT: retq
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entry:
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%cmp = icmp sgt i32 %i, %j
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br i1 %cmp, label %loop_start, label %cond.end
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loop_start:
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br label %while.condthread-pre-split.i
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while.condthread-pre-split.i:
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%.pr.i = load i32, i32* %p, align 4
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br label %while.cond.i
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while.cond.i:
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%0 = phi i32 [ %.pr.i, %while.condthread-pre-split.i ], [ 0, %while.cond.i ]
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%tobool.i = icmp eq i32 %0, 0
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br i1 %tobool.i, label %while.cond.i, label %while.body.i
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while.body.i:
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%.lcssa = phi i32 [ %0, %while.cond.i ]
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%1 = cmpxchg i32* %p, i32 %.lcssa, i32 %.lcssa seq_cst seq_cst
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%2 = extractvalue { i32, i1 } %1, 1
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br i1 %2, label %cond.end.loopexit, label %while.condthread-pre-split.i
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cond.end.loopexit:
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br label %cond.end
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cond.end:
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%cond = phi i32 [ %i, %entry ], [ 0, %cond.end.loopexit ]
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ret i32 %cond
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}
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; This one is an interesting case because CMOV doesn't have a chain
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; operand. Naive attempts to limit cmpxchg EFLAGS use are likely to fail here.
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define i32 @test_feed_cmov(i32* %addr, i32 %desired, i32 %new) nounwind {
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; 32-GOOD-RA-LABEL: test_feed_cmov:
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; 32-GOOD-RA: # %bb.0: # %entry
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; 32-GOOD-RA-NEXT: pushl %ebx
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; 32-GOOD-RA-NEXT: pushl %esi
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; 32-GOOD-RA-NEXT: pushl %eax
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; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %eax
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; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %esi
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; 32-GOOD-RA-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; 32-GOOD-RA-NEXT: lock cmpxchgl %esi, (%ecx)
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; 32-GOOD-RA-NEXT: sete %bl
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; 32-GOOD-RA-NEXT: calll foo
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; 32-GOOD-RA-NEXT: testb %bl, %bl
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; 32-GOOD-RA-NEXT: jne .LBB2_2
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; 32-GOOD-RA-NEXT: # %bb.1: # %entry
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; 32-GOOD-RA-NEXT: movl %eax, %esi
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; 32-GOOD-RA-NEXT: .LBB2_2: # %entry
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; 32-GOOD-RA-NEXT: movl %esi, %eax
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; 32-GOOD-RA-NEXT: addl $4, %esp
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; 32-GOOD-RA-NEXT: popl %esi
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; 32-GOOD-RA-NEXT: popl %ebx
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; 32-GOOD-RA-NEXT: retl
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;
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; 32-FAST-RA-LABEL: test_feed_cmov:
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; 32-FAST-RA: # %bb.0: # %entry
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; 32-FAST-RA-NEXT: pushl %ebx
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; 32-FAST-RA-NEXT: pushl %esi
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; 32-FAST-RA-NEXT: pushl %eax
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; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %esi
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; 32-FAST-RA-NEXT: movl {{[0-9]+}}(%esp), %eax
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; 32-FAST-RA-NEXT: lock cmpxchgl %esi, (%ecx)
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; 32-FAST-RA-NEXT: sete %bl
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; 32-FAST-RA-NEXT: calll foo
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; 32-FAST-RA-NEXT: testb %bl, %bl
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; 32-FAST-RA-NEXT: jne .LBB2_2
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; 32-FAST-RA-NEXT: # %bb.1: # %entry
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; 32-FAST-RA-NEXT: movl %eax, %esi
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; 32-FAST-RA-NEXT: .LBB2_2: # %entry
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; 32-FAST-RA-NEXT: movl %esi, %eax
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; 32-FAST-RA-NEXT: addl $4, %esp
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; 32-FAST-RA-NEXT: popl %esi
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; 32-FAST-RA-NEXT: popl %ebx
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; 32-FAST-RA-NEXT: retl
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;
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; 64-ALL-LABEL: test_feed_cmov:
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; 64-ALL: # %bb.0: # %entry
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; 64-ALL-NEXT: pushq %rbp
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; 64-ALL-NEXT: pushq %rbx
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; 64-ALL-NEXT: pushq %rax
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; 64-ALL-NEXT: movl %edx, %ebx
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; 64-ALL-NEXT: movl %esi, %eax
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; 64-ALL-NEXT: lock cmpxchgl %edx, (%rdi)
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; 64-ALL-NEXT: sete %bpl
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; 64-ALL-NEXT: callq foo
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; 64-ALL-NEXT: testb %bpl, %bpl
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; 64-ALL-NEXT: cmovnel %ebx, %eax
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; 64-ALL-NEXT: addq $8, %rsp
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; 64-ALL-NEXT: popq %rbx
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; 64-ALL-NEXT: popq %rbp
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; 64-ALL-NEXT: retq
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entry:
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%res = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
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%success = extractvalue { i32, i1 } %res, 1
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%rhs = call i32 @foo()
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%ret = select i1 %success, i32 %new, i32 %rhs
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ret i32 %ret
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}
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