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https://github.com/RPCS3/llvm-mirror.git
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4ecaa6ff5f
The logic for this combine is almost identical to the logic for a (sext (sextload x)) combine. This commit factors out the logic so it can be shared by both combines, and corrects the SDLoc assigned in the zext version of the combine. Prior to this patch, for the given test case, we would apply the location associated with the udiv instruction to instructions which perform the load. Part of: llvm.org/PR37262 llvm-svn: 331303
106 lines
3.3 KiB
LLVM
106 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-linux -mattr=-bmi | FileCheck %s --check-prefix=CHECK
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; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=-bmi | FileCheck %s --check-prefix=GNUX32
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; LLVM creates virtual registers for values live across blocks
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; based on the type of the value. Make sure that the extracts
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; here use the GR64_NOREX register class for their result,
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; instead of plain GR64.
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define i64 @foo(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: .cfi_offset %rbx, -24
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: movq %rdi, %rbx
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; CHECK-NEXT: movzbl %bh, %esi
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; CHECK-NEXT: movzbl %ah, %eax
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; CHECK-NEXT: movq %rax, %r10
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; CHECK-NEXT: movzbl %dh, %edx
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; CHECK-NEXT: movzbl %ch, %ebp
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; CHECK-NEXT: movq %r8, %rax
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; CHECK-NEXT: movzbl %ah, %ecx
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; CHECK-NEXT: movq %r9, %rax
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; CHECK-NEXT: movzbl %ah, %edi
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %ebx
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; CHECK-NEXT: addq %r10, %rsi
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; CHECK-NEXT: addq %rbp, %rdx
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; CHECK-NEXT: addq %rsi, %rdx
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; CHECK-NEXT: addq %rdi, %rcx
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; CHECK-NEXT: addq %rbx, %rax
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; CHECK-NEXT: addq %rcx, %rax
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; CHECK-NEXT: addq %rdx, %rax
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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;
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; GNUX32-LABEL: foo:
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; GNUX32: # %bb.0:
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; GNUX32-NEXT: pushq %rbp
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; GNUX32-NEXT: .cfi_def_cfa_offset 16
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; GNUX32-NEXT: pushq %rbx
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; GNUX32-NEXT: .cfi_def_cfa_offset 24
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; GNUX32-NEXT: .cfi_offset %rbx, -24
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; GNUX32-NEXT: .cfi_offset %rbp, -16
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; GNUX32-NEXT: movq %rsi, %rax
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; GNUX32-NEXT: movq %rdi, %rbx
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; GNUX32-NEXT: movzbl %bh, %esi
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; GNUX32-NEXT: movzbl %ah, %eax
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; GNUX32-NEXT: movq %rax, %r10
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; GNUX32-NEXT: movzbl %dh, %edx
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; GNUX32-NEXT: movzbl %ch, %ebp
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; GNUX32-NEXT: movq %r8, %rax
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; GNUX32-NEXT: movzbl %ah, %ecx
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; GNUX32-NEXT: movq %r9, %rax
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; GNUX32-NEXT: movzbl %ah, %edi
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; GNUX32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; GNUX32-NEXT: movzbl {{[0-9]+}}(%esp), %ebx
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; GNUX32-NEXT: addq %r10, %rsi
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; GNUX32-NEXT: addq %rbp, %rdx
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; GNUX32-NEXT: addq %rsi, %rdx
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; GNUX32-NEXT: addq %rdi, %rcx
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; GNUX32-NEXT: addq %rbx, %rax
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; GNUX32-NEXT: addq %rcx, %rax
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; GNUX32-NEXT: addq %rdx, %rax
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; GNUX32-NEXT: popq %rbx
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; GNUX32-NEXT: .cfi_def_cfa_offset 16
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; GNUX32-NEXT: popq %rbp
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; GNUX32-NEXT: .cfi_def_cfa_offset 8
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; GNUX32-NEXT: retq
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%sa = lshr i64 %a, 8
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%A = and i64 %sa, 255
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%sb = lshr i64 %b, 8
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%B = and i64 %sb, 255
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%sc = lshr i64 %c, 8
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%C = and i64 %sc, 255
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%sd = lshr i64 %d, 8
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%D = and i64 %sd, 255
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%se = lshr i64 %e, 8
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%E = and i64 %se, 255
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%sf = lshr i64 %f, 8
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%F = and i64 %sf, 255
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%sg = lshr i64 %g, 8
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%G = and i64 %sg, 255
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%sh = lshr i64 %h, 8
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%H = and i64 %sh, 255
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br label %next
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next:
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%u = add i64 %A, %B
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%v = add i64 %C, %D
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%w = add i64 %E, %F
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%x = add i64 %G, %H
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%y = add i64 %u, %v
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%z = add i64 %w, %x
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%t = add i64 %y, %z
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ret i64 %t
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}
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