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2196dd6cfa
This patch replaces the --x86_extra_scrub command line argument to automatically support a second level of regex-scrubbing if it improves the matching of nearly-identical code patterns. The argument '--extra_scrub' is there now to force extra matching if required. This is mostly useful to help us share 32-bit/64-bit x86 vector tests which only differs by retl/retq instructions, but any scrubber can now technically support this, meaning test checks don't have to be needlessly obfuscated. I've updated some of the existing checks that had been manually run with --x86_extra_scrub, to demonstrate the extra "ret{{[l|q]}}" scrub now only happens when useful, and re-run the sse42-intrinsics file to show extra matches - most sse/avx intrinsics files should be able to now share 32/64 checks. Tested with the opt/analysis scripts as well which share common code - AFAICT the other update scripts use their own versions. Differential Revision: https://reviews.llvm.org/D47485 llvm-svn: 333749
106 lines
4.2 KiB
LLVM
106 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=X86-SSE
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1 --check-prefix=X86-AVX --check-prefix=X86-AVX1
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 --check-prefix=X86-AVX --check-prefix=X86-AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=X64-SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1 --check-prefix=X64-AVX --check-prefix=X64-AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 --check-prefix=X64-AVX --check-prefix=X64-AVX2
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define <4 x i32> @trunc_ashr_v4i64(<4 x i64> %a) nounwind {
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; SSE-LABEL: trunc_ashr_v4i64:
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; SSE: # %bb.0:
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
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; SSE-NEXT: psrad $31, %xmm0
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
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; SSE-NEXT: packssdw %xmm1, %xmm0
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; SSE-NEXT: ret{{[l|q]}}
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;
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; AVX1-LABEL: trunc_ashr_v4i64:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm1
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; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm0
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; AVX1-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: ret{{[l|q]}}
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;
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; AVX2-LABEL: trunc_ashr_v4i64:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX2-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: ret{{[l|q]}}
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%1 = ashr <4 x i64> %a, <i64 63, i64 63, i64 63, i64 63>
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%2 = trunc <4 x i64> %1 to <4 x i32>
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ret <4 x i32> %2
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}
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define <8 x i16> @trunc_ashr_v8i32(<8 x i32> %a) nounwind {
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; SSE-LABEL: trunc_ashr_v8i32:
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; SSE: # %bb.0:
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: psrad $31, %xmm0
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; SSE-NEXT: packssdw %xmm1, %xmm0
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; SSE-NEXT: ret{{[l|q]}}
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;
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; AVX1-LABEL: trunc_ashr_v8i32:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpsrad $31, %xmm1, %xmm1
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; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0
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; AVX1-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: ret{{[l|q]}}
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;
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; AVX2-LABEL: trunc_ashr_v8i32:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsrad $31, %ymm0, %ymm0
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; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX2-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: ret{{[l|q]}}
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%1 = ashr <8 x i32> %a, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
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%2 = trunc <8 x i32> %1 to <8 x i16>
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ret <8 x i16> %2
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}
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define <8 x i16> @trunc_ashr_v4i32_icmp_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
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; X86-SSE-LABEL: trunc_ashr_v4i32_icmp_v4i32:
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; X86-SSE: # %bb.0:
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; X86-SSE-NEXT: psrad $31, %xmm0
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; X86-SSE-NEXT: pcmpgtd {{\.LCPI.*}}, %xmm1
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; X86-SSE-NEXT: packssdw %xmm1, %xmm0
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; X86-SSE-NEXT: retl
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;
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; X86-AVX-LABEL: trunc_ashr_v4i32_icmp_v4i32:
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; X86-AVX: # %bb.0:
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; X86-AVX-NEXT: vpsrad $31, %xmm0, %xmm0
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; X86-AVX-NEXT: vpcmpgtd {{\.LCPI.*}}, %xmm1, %xmm1
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; X86-AVX-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
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; X86-AVX-NEXT: retl
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;
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; X64-SSE-LABEL: trunc_ashr_v4i32_icmp_v4i32:
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; X64-SSE: # %bb.0:
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; X64-SSE-NEXT: psrad $31, %xmm0
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; X64-SSE-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
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; X64-SSE-NEXT: packssdw %xmm1, %xmm0
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; X64-SSE-NEXT: retq
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;
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; X64-AVX-LABEL: trunc_ashr_v4i32_icmp_v4i32:
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; X64-AVX: # %bb.0:
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; X64-AVX-NEXT: vpsrad $31, %xmm0, %xmm0
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; X64-AVX-NEXT: vpcmpgtd {{.*}}(%rip), %xmm1, %xmm1
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; X64-AVX-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
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; X64-AVX-NEXT: retq
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%1 = ashr <4 x i32> %a, <i32 31, i32 31, i32 31, i32 31>
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%2 = icmp sgt <4 x i32> %b, <i32 1, i32 16, i32 255, i32 65535>
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%3 = sext <4 x i1> %2 to <4 x i32>
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%4 = shufflevector <4 x i32> %1, <4 x i32> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%5 = trunc <8 x i32> %4 to <8 x i16>
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ret <8 x i16> %5
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}
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