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7e822ea5f7
64-bit MMX vector generation usually ends up lowering into SSE instructions before being spilled/reloaded as a MMX type. This patch creates a MMX vector from MMX source values, taking the lowest element from each source and constructing broadcasts/build_vectors with direct calls to the MMX PUNPCKL/PSHUFW intrinsics. We're missing a few consecutive load combines that could be handled in a future patch if that would be useful - my main interest here is just avoiding a lot of the MMX/SSE crossover. Differential Revision: https://reviews.llvm.org/D43618 llvm-svn: 327247
76 lines
3.0 KiB
LLVM
76 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefixes=X86,X86-SSE
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+avx2 | FileCheck %s --check-prefixes=X86,X86-AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefixes=X64,X64-SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+avx2 | FileCheck %s --check-prefixes=X64,X64-AVX
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define i32 @PR29222(i32) nounwind {
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; X86-SSE-LABEL: PR29222:
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; X86-SSE: # %bb.0:
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; X86-SSE-NEXT: pushl %ebp
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; X86-SSE-NEXT: movl %esp, %ebp
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; X86-SSE-NEXT: andl $-8, %esp
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; X86-SSE-NEXT: subl $8, %esp
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; X86-SSE-NEXT: movd 8(%ebp), %mm0
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; X86-SSE-NEXT: pshufw $68, %mm0, %mm0 # mm0 = mm0[0,1,0,1]
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; X86-SSE-NEXT: packsswb %mm0, %mm0
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; X86-SSE-NEXT: movq %mm0, (%esp)
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; X86-SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; X86-SSE-NEXT: packsswb %xmm0, %xmm0
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; X86-SSE-NEXT: movd %xmm0, %eax
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; X86-SSE-NEXT: movl %ebp, %esp
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; X86-SSE-NEXT: popl %ebp
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; X86-SSE-NEXT: retl
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;
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; X86-AVX-LABEL: PR29222:
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; X86-AVX: # %bb.0:
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; X86-AVX-NEXT: pushl %ebp
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; X86-AVX-NEXT: movl %esp, %ebp
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; X86-AVX-NEXT: andl $-8, %esp
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; X86-AVX-NEXT: subl $8, %esp
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; X86-AVX-NEXT: movd 8(%ebp), %mm0
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; X86-AVX-NEXT: pshufw $68, %mm0, %mm0 # mm0 = mm0[0,1,0,1]
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; X86-AVX-NEXT: packsswb %mm0, %mm0
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; X86-AVX-NEXT: movq %mm0, (%esp)
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; X86-AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
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; X86-AVX-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
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; X86-AVX-NEXT: vmovd %xmm0, %eax
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; X86-AVX-NEXT: movl %ebp, %esp
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; X86-AVX-NEXT: popl %ebp
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; X86-AVX-NEXT: retl
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;
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; X64-SSE-LABEL: PR29222:
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; X64-SSE: # %bb.0:
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; X64-SSE-NEXT: movd %edi, %mm0
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; X64-SSE-NEXT: pshufw $68, %mm0, %mm0 # mm0 = mm0[0,1,0,1]
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; X64-SSE-NEXT: packsswb %mm0, %mm0
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; X64-SSE-NEXT: movq2dq %mm0, %xmm0
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; X64-SSE-NEXT: packsswb %xmm0, %xmm0
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; X64-SSE-NEXT: movd %xmm0, %eax
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; X64-SSE-NEXT: retq
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;
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; X64-AVX-LABEL: PR29222:
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; X64-AVX: # %bb.0:
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; X64-AVX-NEXT: movd %edi, %mm0
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; X64-AVX-NEXT: pshufw $68, %mm0, %mm0 # mm0 = mm0[0,1,0,1]
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; X64-AVX-NEXT: packsswb %mm0, %mm0
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; X64-AVX-NEXT: movq2dq %mm0, %xmm0
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; X64-AVX-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
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; X64-AVX-NEXT: vmovd %xmm0, %eax
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; X64-AVX-NEXT: retq
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%2 = insertelement <2 x i32> undef, i32 %0, i32 0
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%3 = shufflevector <2 x i32> %2, <2 x i32> undef, <2 x i32> zeroinitializer
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%4 = bitcast <2 x i32> %3 to x86_mmx
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%5 = tail call x86_mmx @llvm.x86.mmx.packsswb(x86_mmx %4, x86_mmx %4)
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%6 = bitcast x86_mmx %5 to i64
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%7 = insertelement <2 x i64> undef, i64 %6, i32 0
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%8 = bitcast <2 x i64> %7 to <8 x i16>
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%9 = tail call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %8, <8 x i16> undef)
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%10 = bitcast <16 x i8> %9 to <4 x i32>
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%11 = extractelement <4 x i32> %10, i32 0
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ret i32 %11
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}
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declare x86_mmx @llvm.x86.mmx.packsswb(x86_mmx, x86_mmx)
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declare <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16>, <8 x i16>)
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