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8532085a99
We were previously prefering ZEXTLOAD over EXTLOAD if it is legal. This triggers during X86's promotion of i16->i32. Not sure about other targets. Using ZEXTLOAD can prevent folding it to SEXTLOAD later if we were to promote a sign extended operand like we would need for SRA. However, X86 doesn't currently promote i16 SRA. I was looking into doing that which is how I found this issue. This is also blocking our ability to fold 4 byte aligned EXTLOADs with "loadi32". This is what caused most of the test changes here. Differential Revision: https://reviews.llvm.org/D45585#inline-402825 llvm-svn: 330781
39 lines
1.2 KiB
LLVM
39 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.12.0"
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@a = common local_unnamed_addr global i16 0, align 4
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@b = common local_unnamed_addr global i16 0, align 4
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define i32 @PR32420() {
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; CHECK-LABEL: PR32420:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq _a@{{.*}}(%rip), %rcx
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; CHECK-NEXT: movzwl (%rcx), %eax
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: shll $12, %edx
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; CHECK-NEXT: sarw $12, %dx
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; CHECK-NEXT: movq _b@{{.*}}(%rip), %rsi
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; CHECK-NEXT: orw (%rsi), %dx
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; CHECK-NEXT: movl (%rcx), %ecx
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; CHECK-NEXT: shll $12, %ecx
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; CHECK-NEXT: sarw $12, %cx
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; CHECK-NEXT: andl %edx, %ecx
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; CHECK-NEXT: movw %cx, (%rsi)
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; CHECK-NEXT: retq
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%load2 = load i16, i16* @a, align 4
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%shl3 = shl i16 %load2, 12
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%ashr4 = ashr i16 %shl3, 12
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%t2 = load volatile i16, i16* @b, align 4
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%conv8 = or i16 %t2, %ashr4
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%load9 = load i16, i16* @a, align 4
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%shl10 = shl i16 %load9, 12
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%ashr11 = ashr i16 %shl10, 12
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%and = and i16 %conv8, %ashr11
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store i16 %and, i16* @b, align 4
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%cast1629 = zext i16 %load2 to i32
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ret i32 %cast1629
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}
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