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3633380341
Summary: In SelectionDAG, when a store is immediately chained to another store to the same address, elide the first store as it has no observable effects. This is causes small improvements dealing with intrinsics lowered to stores. Test notes: * Many testcases overwrite store addresses multiple times and needed minor changes, mainly making stores volatile to prevent the optimization from optimizing the test away. * Many X86 test cases optimized out instructions associated with associated with va_start. * Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has dependencies to check and can probably be removed and potentially replaced with another test. Reviewers: rnk, john.brawn Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33206 llvm-svn: 303198
41 lines
1.1 KiB
LLVM
41 lines
1.1 KiB
LLVM
; RUN: llc -mcpu=generic -mtriple=i686-pc-windows-msvc -mattr=+sse < %s | FileCheck %s
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; Check proper alignment of spilled vector
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; CHECK-LABEL: spill_ok
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; CHECK: subl $32, %esp
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; CHECK: movaps %xmm3, (%esp)
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; CHECK: movl $0, 16(%esp)
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; CHECK: calll _bar
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define void @spill_ok(i32, <16 x float> *) {
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entry:
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%2 = alloca i32, i32 %0
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%3 = load <16 x float>, <16 x float> * %1, align 64
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tail call void @bar(<16 x float> %3, i32 0) nounwind
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ret void
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}
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declare void @bar(<16 x float> %a, i32 %b)
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; Check that proper alignment of spilled vector does not affect vargs
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; CHECK-LABEL: vargs_not_affected
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; CHECK: movl 28(%ebp), %eax
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define i32 @vargs_not_affected(<4 x float> %v, i8* %f, ...) {
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entry:
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%ap = alloca i8*, align 4
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%0 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %0)
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%argp.cur = load i8*, i8** %ap, align 4
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%argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
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store i8* %argp.next, i8** %ap, align 4
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%1 = bitcast i8* %argp.cur to i32*
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%2 = load i32, i32* %1, align 4
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call void @llvm.va_end(i8* %0)
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ret i32 %2
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}
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declare void @llvm.va_start(i8*)
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declare void @llvm.va_end(i8*)
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