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96ee5e4899
Our 16 bit support is assembler-only + the terrible hack that is .code16gcc. Simply using 32 bit registers does the right thing for the latter. Fixes PR32681. llvm-svn: 300429
28 lines
605 B
LLVM
28 lines
605 B
LLVM
; RUN: llc < %s | FileCheck %s
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target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
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target triple = "i386-unknown-linux-code16"
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; Function Attrs: nounwind
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define i32 @main() #0 {
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%retval = alloca i32, align 4
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store i32 0, i32* %retval, align 4
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ret i32 0
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}
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; CHECK: .code16
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; CHECK-LABEL: main
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define i64 @foo(i32 %index) #0 {
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%asm = tail call i64 asm "rdmsr", "=A,{cx},~{dirflag},~{fpsr},~{flags}"(i32 %index)
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ret i64 %asm
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}
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; CHECK-LABEL: foo
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; CHECK: rdmsr
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attributes #0 = { nounwind }
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!llvm.ident = !{!0}
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!0 = !{!"clang version 3.9.0 (trunk 265439) (llvm/trunk 265567)"}
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