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104 lines
3.8 KiB
C++
104 lines
3.8 KiB
C++
//===- SPURegisterInfo.h - Cell SPU Register Information Impl ----*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Cell SPU implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPU_REGISTERINFO_H
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#define SPU_REGISTERINFO_H
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#include "SPU.h"
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#include "SPUGenRegisterInfo.h.inc"
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namespace llvm {
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class SPUSubtarget;
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class TargetInstrInfo;
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class Type;
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class SPURegisterInfo : public SPUGenRegisterInfo {
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private:
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const SPUSubtarget &Subtarget;
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const TargetInstrInfo &TII;
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//! Predicate: Does the machine function use the link register?
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bool usesLR(MachineFunction &MF) const;
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public:
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SPURegisterInfo(const SPUSubtarget &subtarget, const TargetInstrInfo &tii);
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//! Translate a register's enum value to a register number
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/*!
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This method translates a register's enum value to it's regiser number,
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e.g. SPU::R14 -> 14.
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*/
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static unsigned getRegisterNumbering(unsigned RegEnum);
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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virtual const TargetRegisterClass *
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getPointerRegClass(unsigned Kind = 0) const;
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//! Return the array of callee-saved registers
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virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const;
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//! Return the register class array of the callee-saved registers
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virtual const TargetRegisterClass* const *
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getCalleeSavedRegClasses(const MachineFunction *MF) const;
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//! Return the reserved registers
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BitVector getReservedRegs(const MachineFunction &MF) const;
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//! Prediate: Target has dedicated frame pointer
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bool hasFP(const MachineFunction &MF) const;
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//! Eliminate the call frame setup pseudo-instructions
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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//! Convert frame indicies into machine operands
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unsigned eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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int *Value = NULL,
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RegScavenger *RS = NULL) const;
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//! Determine the frame's layour
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void determineFrameLayout(MachineFunction &MF) const;
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS = NULL) const;
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//! Emit the function prologue
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void emitPrologue(MachineFunction &MF) const;
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//! Emit the function epilogue
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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//! Get return address register (LR, aka R0)
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unsigned getRARegister() const;
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//! Get the stack frame register (SP, aka R1)
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unsigned getFrameRegister(const MachineFunction &MF) const;
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//! Perform target-specific stack frame setup.
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void getInitialFrameState(std::vector<MachineMove> &Moves) const;
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//------------------------------------------------------------------------
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// New methods added:
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//------------------------------------------------------------------------
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//! Return the array of argument passing registers
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/*!
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\note The size of this array is returned by getArgRegsSize().
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*/
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static const unsigned *getArgRegs();
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//! Return the size of the argument passing register array
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static unsigned getNumArgRegs();
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//! Get DWARF debugging register number
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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};
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} // end namespace llvm
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#endif
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