Alex Bradbury 560294c13d [RISCV] Prepare for the use of variable-sized register classes ... While parameterising by XLen, also take the opportunity to clean up the formatting of the RISCV .td files. This commit unifies the in-tree code with my patchset at <https://github.com/lowrisc/riscv-llvm>. llvm-svn: 316159		2017-10-19 14:29:03 +00:00
..
CMakeLists.txt	[RISCV] Add common fixups and relocations	2017-09-28 08:26:24 +00:00
LLVMBuild.txt	[RISCV] Add RISCVInstPrinter and basic MC assembler tests	2017-08-15 13:08:29 +00:00
RISCVAsmBackend.cpp	[RISCV] Fix build after r315327	2017-10-11 12:09:06 +00:00
RISCVBaseInfo.h	[RISCV] Prepare for the use of variable-sized register classes	2017-10-19 14:29:03 +00:00
RISCVELFObjectWriter.cpp	[RISCV] Bugfix createRISCVELFObjectWriter	2017-10-18 16:11:31 +00:00
RISCVFixupKinds.h	[RISCV] Add common fixups and relocations	2017-09-28 08:26:24 +00:00
RISCVMCAsmInfo.cpp	Distinguish between code pointer size and DataLayout::getPointerSize() in DWARF info generation	2017-04-17 17:41:25 +00:00
RISCVMCAsmInfo.h
RISCVMCCodeEmitter.cpp	[RISCV] Prepare for the use of variable-sized register classes	2017-10-19 14:29:03 +00:00
RISCVMCExpr.cpp	[RISCV] Add common fixups and relocations	2017-09-28 08:26:24 +00:00
RISCVMCExpr.h	[RISCV] Add common fixups and relocations	2017-09-28 08:26:24 +00:00
RISCVMCTargetDesc.cpp	[RISCV] Prepare for the use of variable-sized register classes	2017-10-19 14:29:03 +00:00
RISCVMCTargetDesc.h	[RISCV] Fix build after r315327	2017-10-11 12:09:06 +00:00