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c2664c73ba
This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188
171 lines
5.3 KiB
C++
171 lines
5.3 KiB
C++
//===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that RISCV uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVISelLowering.h"
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#include "RISCV.h"
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#include "RISCVRegisterInfo.h"
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#include "RISCVSubtarget.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/DiagnosticInfo.h"
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#include "llvm/IR/DiagnosticPrinter.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-lower"
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RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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const RISCVSubtarget &STI)
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: TargetLowering(TM), Subtarget(STI) {
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MVT XLenVT = Subtarget.getXLenVT();
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// Set up the register classes.
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addRegisterClass(XLenVT, &RISCV::GPRRegClass);
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// Compute derived properties from the register classes.
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computeRegisterProperties(STI.getRegisterInfo());
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setStackPointerRegisterToSaveRestore(RISCV::X2);
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// TODO: add all necessary setOperationAction calls.
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setBooleanContents(ZeroOrOneBooleanContent);
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// Function alignments (log2).
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setMinFunctionAlignment(3);
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setPrefFunctionAlignment(3);
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}
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SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
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SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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default:
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report_fatal_error("unimplemented operand");
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}
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}
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// Calling Convention Implementation.
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#include "RISCVGenCallingConv.inc"
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// Transform physical registers into virtual registers.
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SDValue RISCVTargetLowering::LowerFormalArguments(
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SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
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SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
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switch (CallConv) {
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default:
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report_fatal_error("Unsupported calling convention");
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case CallingConv::C:
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break;
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}
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MachineFunction &MF = DAG.getMachineFunction();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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MVT XLenVT = Subtarget.getXLenVT();
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if (IsVarArg)
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report_fatal_error("VarArg not supported");
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// Assign locations to all of the incoming arguments.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV32);
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for (auto &VA : ArgLocs) {
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if (!VA.isRegLoc())
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report_fatal_error("Defined with too many args");
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// Arguments passed in registers.
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EVT RegVT = VA.getLocVT();
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if (RegVT != XLenVT) {
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DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: "
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<< RegVT.getEVTString() << "\n");
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report_fatal_error("unhandled argument type");
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}
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const unsigned VReg =
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RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
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RegInfo.addLiveIn(VA.getLocReg(), VReg);
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SDValue ArgIn = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
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InVals.push_back(ArgIn);
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}
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return Chain;
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}
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SDValue
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RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SDLoc &DL, SelectionDAG &DAG) const {
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if (IsVarArg) {
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report_fatal_error("VarArg not supported");
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}
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// Stores the assignment of the return value to a location.
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SmallVector<CCValAssign, 16> RVLocs;
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// Info about the registers and stack slot.
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CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
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*DAG.getContext());
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CCInfo.AnalyzeReturn(Outs, RetCC_RISCV32);
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SDValue Flag;
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SmallVector<SDValue, 4> RetOps(1, Chain);
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// Copy the result values into the output registers.
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for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) {
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CCValAssign &VA = RVLocs[i];
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assert(VA.isRegLoc() && "Can only return in registers!");
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Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
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// Guarantee that all emitted copies are stuck together.
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Flag = Chain.getValue(1);
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RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
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}
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RetOps[0] = Chain; // Update chain.
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// Add the flag if we have it.
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if (Flag.getNode()) {
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RetOps.push_back(Flag);
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}
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return DAG.getNode(RISCVISD::RET_FLAG, DL, MVT::Other, RetOps);
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}
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const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch ((RISCVISD::NodeType)Opcode) {
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case RISCVISD::FIRST_NUMBER:
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break;
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case RISCVISD::RET_FLAG:
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return "RISCVISD::RET_FLAG";
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}
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return nullptr;
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}
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