1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-30 23:42:52 +01:00
llvm-mirror/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
JF Bastien cb60eaba94 Enable FastISel on ARM for Linux and NaCl, not MCJIT
This is a resubmit of r182877, which was reverted because it broken
MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only
enabled for iOS. I've CC'ed people from the original review and revert.

FastISel was only enabled for iOS ARM and Thumb2, this patch enables it
for ARM (not Thumb2) on Linux and NaCl, but not MCJIT.

Thumb2 support needs a bit more work, mainly around register class
restrictions.

The patch punts to SelectionDAG when doing TLS relocation on non-Darwin
targets. I will fix this and other FastISel-to-SelectionDAG failures in
a separate patch.

The patch also forces FastISel to retain frame pointers: iOS always
keeps them for backtracking (so emitted code won't change because of
this), but Linux was getting much worse code that was incorrect when
using big frames (such as test-suite's lencod). I'll also fix this in a
later patch, it will probably require a peephole so that FastISel
doesn't rematerialize frame pointers back-to-back.

The test changes are straightforward, similar to:
  http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html
They also add a vararg test that got dropped in that change.

I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0
and all the tests pass. All the tests also pass on x86 make check-all. I
also re-ran the check-all tests that failed on ARM, and they all seem to
pass.

llvm-svn: 183966
2013-06-14 02:49:43 +00:00

151 lines
3.8 KiB
LLVM

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
; rdar://10418009
define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM: t1
%add.ptr = getelementptr inbounds i16* %a, i64 -8
%0 = load i16* %add.ptr, align 2
; ARM: ldrh r0, [r0, #-16]
ret i16 %0
}
define zeroext i16 @t2(i16* nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM: t2
%add.ptr = getelementptr inbounds i16* %a, i64 -16
%0 = load i16* %add.ptr, align 2
; ARM: ldrh r0, [r0, #-32]
ret i16 %0
}
define zeroext i16 @t3(i16* nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM: t3
%add.ptr = getelementptr inbounds i16* %a, i64 -127
%0 = load i16* %add.ptr, align 2
; ARM: ldrh r0, [r0, #-254]
ret i16 %0
}
define zeroext i16 @t4(i16* nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM: t4
%add.ptr = getelementptr inbounds i16* %a, i64 -128
%0 = load i16* %add.ptr, align 2
; ARM: mvn r{{[1-9]}}, #255
; ARM: add r0, r0, r{{[1-9]}}
; ARM: ldrh r0, [r0]
ret i16 %0
}
define zeroext i16 @t5(i16* nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM: t5
%add.ptr = getelementptr inbounds i16* %a, i64 8
%0 = load i16* %add.ptr, align 2
; ARM: ldrh r0, [r0, #16]
ret i16 %0
}
define zeroext i16 @t6(i16* nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM: t6
%add.ptr = getelementptr inbounds i16* %a, i64 16
%0 = load i16* %add.ptr, align 2
; ARM: ldrh r0, [r0, #32]
ret i16 %0
}
define zeroext i16 @t7(i16* nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM: t7
%add.ptr = getelementptr inbounds i16* %a, i64 127
%0 = load i16* %add.ptr, align 2
; ARM: ldrh r0, [r0, #254]
ret i16 %0
}
define zeroext i16 @t8(i16* nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM: t8
%add.ptr = getelementptr inbounds i16* %a, i64 128
%0 = load i16* %add.ptr, align 2
; ARM: add r0, r0, #256
; ARM: ldrh r0, [r0]
ret i16 %0
}
define void @t9(i16* nocapture %a) nounwind uwtable ssp {
entry:
; ARM: t9
%add.ptr = getelementptr inbounds i16* %a, i64 -8
store i16 0, i16* %add.ptr, align 2
; ARM: strh r1, [r0, #-16]
ret void
}
; mvn r1, #255
; strh r2, [r0, r1]
define void @t10(i16* nocapture %a) nounwind uwtable ssp {
entry:
; ARM: t10
%add.ptr = getelementptr inbounds i16* %a, i64 -128
store i16 0, i16* %add.ptr, align 2
; ARM: mvn r{{[1-9]}}, #255
; ARM: add r0, r0, r{{[1-9]}}
; ARM: strh r{{[1-9]}}, [r0]
ret void
}
define void @t11(i16* nocapture %a) nounwind uwtable ssp {
entry:
; ARM: t11
%add.ptr = getelementptr inbounds i16* %a, i64 8
store i16 0, i16* %add.ptr, align 2
; ARM: strh r{{[1-9]}}, [r0, #16]
ret void
}
; mov r1, #256
; strh r2, [r0, r1]
define void @t12(i16* nocapture %a) nounwind uwtable ssp {
entry:
; ARM: t12
%add.ptr = getelementptr inbounds i16* %a, i64 128
store i16 0, i16* %add.ptr, align 2
; ARM: add r0, r0, #256
; ARM: strh r{{[1-9]}}, [r0]
ret void
}
define signext i8 @t13(i8* nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM: t13
%add.ptr = getelementptr inbounds i8* %a, i64 -8
%0 = load i8* %add.ptr, align 2
; ARM: ldrsb r0, [r0, #-8]
ret i8 %0
}
define signext i8 @t14(i8* nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM: t14
%add.ptr = getelementptr inbounds i8* %a, i64 -255
%0 = load i8* %add.ptr, align 2
; ARM: ldrsb r0, [r0, #-255]
ret i8 %0
}
define signext i8 @t15(i8* nocapture %a) nounwind uwtable readonly ssp {
entry:
; ARM: t15
%add.ptr = getelementptr inbounds i8* %a, i64 -256
%0 = load i8* %add.ptr, align 2
; ARM: mvn r{{[1-9]}}, #255
; ARM: add r0, r0, r{{[1-9]}}
; ARM: ldrsb r0, [r0]
ret i8 %0
}