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237 lines
8.3 KiB
C++
237 lines
8.3 KiB
C++
//===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==//
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//
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// This file describes the target machine instructions to the code generator.
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//
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//===---------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_MACHINEINSTRINFO_H
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#define LLVM_TARGET_MACHINEINSTRINFO_H
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/DataTypes.h"
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#include <vector>
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class MachineInstrDescriptor;
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class TmpInstruction;
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class MachineInstr;
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class Value;
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class Instruction;
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typedef int InstrSchedClass;
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// Global variable holding an array of descriptors for machine instructions.
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// The actual object needs to be created separately for each target machine.
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// This variable is initialized and reset by class MachineInstrInfo.
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//
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// FIXME: This should be a property of the target so that more than one target
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// at a time can be active...
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//
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extern const MachineInstrDescriptor *TargetInstrDescriptors;
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//---------------------------------------------------------------------------
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// struct MachineInstrDescriptor:
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// Predefined information about each machine instruction.
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// Designed to initialized statically.
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//
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// class MachineInstructionInfo
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// Interface to description of machine instructions
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//
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//---------------------------------------------------------------------------
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const unsigned int M_NOP_FLAG = 1;
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const unsigned int M_BRANCH_FLAG = 1 << 1;
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const unsigned int M_CALL_FLAG = 1 << 2;
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const unsigned int M_RET_FLAG = 1 << 3;
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const unsigned int M_ARITH_FLAG = 1 << 4;
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const unsigned int M_CC_FLAG = 1 << 6;
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const unsigned int M_LOGICAL_FLAG = 1 << 6;
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const unsigned int M_INT_FLAG = 1 << 7;
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const unsigned int M_FLOAT_FLAG = 1 << 8;
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const unsigned int M_CONDL_FLAG = 1 << 9;
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const unsigned int M_LOAD_FLAG = 1 << 10;
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const unsigned int M_PREFETCH_FLAG = 1 << 11;
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const unsigned int M_STORE_FLAG = 1 << 12;
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const unsigned int M_DUMMY_PHI_FLAG = 1 << 13;
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struct MachineInstrDescriptor {
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string opCodeString; // Assembly language mnemonic for the opcode.
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int numOperands; // Number of args; -1 if variable #args
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int resultPos; // Position of the result; -1 if no result
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unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0.
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bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
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// smallest -ve value is -(maxImmedConst+1).
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unsigned int numDelaySlots; // Number of delay slots after instruction
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unsigned int latency; // Latency in machine cycles
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InstrSchedClass schedClass; // enum identifying instr sched class
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unsigned int iclass; // flags identifying machine instr class
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};
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class MachineInstrInfo : public NonCopyableV {
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protected:
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const MachineInstrDescriptor* desc; // raw array to allow static init'n
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unsigned int descSize; // number of entries in the desc array
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unsigned int numRealOpCodes; // number of non-dummy op codes
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public:
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MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize,
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unsigned numRealOpCodes);
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virtual ~MachineInstrInfo();
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unsigned getNumRealOpCodes() const { return numRealOpCodes; }
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unsigned getNumTotalOpCodes() const { return descSize; }
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const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const {
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assert(opCode >= 0 && opCode < (int)descSize);
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return desc[opCode];
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}
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int getNumOperands(MachineOpCode opCode) const {
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return getDescriptor(opCode).numOperands;
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}
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int getResultPos(MachineOpCode opCode) const {
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return getDescriptor(opCode).resultPos;
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}
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unsigned getNumDelaySlots(MachineOpCode opCode) const {
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return getDescriptor(opCode).numDelaySlots;
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}
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InstrSchedClass getSchedClass(MachineOpCode opCode) const {
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return getDescriptor(opCode).schedClass;
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}
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//
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// Query instruction class flags according to the machine-independent
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// flags listed above.
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//
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unsigned int getIClass(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass;
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}
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bool isNop(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_NOP_FLAG;
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}
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bool isBranch(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_BRANCH_FLAG;
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}
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bool isCall(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_CALL_FLAG;
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}
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bool isReturn(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_RET_FLAG;
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}
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bool isControlFlow(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_BRANCH_FLAG
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|| getDescriptor(opCode).iclass & M_CALL_FLAG
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|| getDescriptor(opCode).iclass & M_RET_FLAG;
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}
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bool isArith(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_RET_FLAG;
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}
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bool isCCInstr(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_CC_FLAG;
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}
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bool isLogical(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOGICAL_FLAG;
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}
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bool isIntInstr(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_INT_FLAG;
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}
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bool isFloatInstr(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_FLOAT_FLAG;
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}
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bool isConditional(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_CONDL_FLAG;
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}
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bool isLoad(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOAD_FLAG;
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}
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bool isPrefetch(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
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}
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bool isLoadOrPrefetch(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOAD_FLAG
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|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
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}
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bool isStore(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_STORE_FLAG;
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}
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bool isMemoryAccess(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOAD_FLAG
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|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG
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|| getDescriptor(opCode).iclass & M_STORE_FLAG;
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}
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bool isDummyPhiInstr(const MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
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}
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// delete this later *******
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bool isPhi(const MachineOpCode opCode) { return isDummyPhiInstr(opCode); }
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// Check if an instruction can be issued before its operands are ready,
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// or if a subsequent instruction that uses its result can be issued
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// before the results are ready.
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// Default to true since most instructions on many architectures allow this.
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//
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virtual bool hasOperandInterlock(MachineOpCode opCode) const {
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return true;
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}
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virtual bool hasResultInterlock(MachineOpCode opCode) const {
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return true;
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}
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//
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// Latencies for individual instructions and instruction pairs
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//
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virtual int minLatency(MachineOpCode opCode) const {
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return getDescriptor(opCode).latency;
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}
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virtual int maxLatency(MachineOpCode opCode) const {
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return getDescriptor(opCode).latency;
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}
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// Check if the specified constant fits in the immediate field
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// of this machine instruction
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//
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virtual bool constantFitsInImmedField(MachineOpCode opCode,
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int64_t intValue) const;
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// Return the largest +ve constant that can be held in the IMMMED field
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// of this machine instruction.
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// isSignExtended is set to true if the value is sign-extended before use
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// (this is true for all immediate fields in SPARC instructions).
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// Return 0 if the instruction has no IMMED field.
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//
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virtual uint64_t maxImmedConstant(MachineOpCode opCode,
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bool &isSignExtended) const {
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isSignExtended = getDescriptor(opCode).immedIsSignExtended;
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return getDescriptor(opCode).maxImmedConst;
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}
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//-------------------------------------------------------------------------
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// Code generation support for creating individual machine instructions
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//-------------------------------------------------------------------------
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// Create an instruction sequence to put the constant `val' into
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// the virtual register `dest'. `val' may be a ConstPoolVal or a
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// GlobalValue, viz., the constant address of a global variable or function.
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// The generated instructions are returned in `minstrVec'.
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// Any temp. registers (TmpInstruction) created are returned in `tempVec'.
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//
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virtual void CreateCodeToLoadConst(Value* val,
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Instruction* dest,
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vector<MachineInstr*>& minstrVec,
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vector<TmpInstruction*>& temps) const =0;
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};
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#endif
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