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95037fa9f6
Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
41 lines
1.1 KiB
LLVM
41 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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define i32 @indirectbr(i8* %target) nounwind {
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; RV32I-LABEL: indirectbr:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: jr a0
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; RV32I-NEXT: .LBB0_1: # %test_label
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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indirectbr i8* %target, [label %test_label]
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test_label:
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br label %ret
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ret:
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ret i32 0
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}
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define i32 @indirectbr_with_offset(i8* %a) nounwind {
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; RV32I-LABEL: indirectbr_with_offset:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: jr 1380(a0)
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; RV32I-NEXT: .LBB1_1: # %test_label
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%target = getelementptr inbounds i8, i8* %a, i32 1380
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indirectbr i8* %target, [label %test_label]
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test_label:
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br label %ret
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ret:
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ret i32 0
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}
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