Artem Tamazov baaf0740cf [test/AMDGPU] Square-braced-syntax for registers: add macro test/example. ...

Test added as per discussion in http://reviews.llvm.org/D20588.
The macro is just a demonstration, useless in practice.
Coding style fixes.

Differential Revision: http://reviews.llvm.org/D20797

llvm-svn: 271675

2016-06-03 14:41:17 +00:00

..

AArch64

RAS extensions are part of ARMv8.2-A. This change enables them by introducing a

2016-06-03 14:03:27 +00:00

AMDGPU

[test/AMDGPU] Square-braced-syntax for registers: add macro test/example.

2016-06-03 14:41:17 +00:00

ARM

RAS extensions are part of ARMv8.2-A. This change enables them by introducing a

2016-06-03 14:03:27 +00:00

AsmParser

Ignore Lexing errors in macro body definitions

2016-06-02 17:15:05 +00:00

COFF

Fix a crash when producing COFF.

2016-05-30 20:18:53 +00:00

Disassembler

RAS extensions are part of ARMv8.2-A. This change enables them by introducing a

2016-06-03 14:03:27 +00:00

ELF

Fix production of R_X86_64_GOTPCRELX/R_X86_64_REX_GOTPCRELX.

2016-05-28 15:51:38 +00:00

Hexagon

[Hexagon] Use pipe instead of temporary files in tests

2016-05-20 14:01:34 +00:00

Lanai

[lanai] isBrImm should accept any non-constant immediate.

2016-03-31 17:58:55 +00:00

MachO

CodeGen: Use PLT relocations for relative references to unnamed_addr functions.

2016-04-22 20:40:10 +00:00

Markup

MC: Simple example parser for MC assembly markup.

2012-10-31 23:24:13 +00:00

Mips

[mips] Remove CPU-only triples from llvm-objdump commands.

2016-06-03 10:22:22 +00:00

PowerPC

Don't pass relocation-model= to tests that don't need it.

2016-05-18 00:27:17 +00:00

Sparc

Don't pass a Reloc::Model to MC.

2016-05-18 11:58:50 +00:00

SystemZ

[SystemZ] Support LRVH and STRVH opcodes

2016-05-16 20:32:22 +00:00

X86

[x86] avoid printing unnecessary sign bits of hex immediates in asm comments (PR20347)

2016-05-28 14:58:37 +00:00