mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 02:52:53 +02:00
1643bee451
In the ARM backend, for historical reasons we have only some targets using Machine Scheduling. The rest use the old list scheduler as they are using itinaries and the list scheduler seems to produce better code (and not crash running out of register on v6m codes). So whether to use the MIScheduler or not is checked at runtime from the subtarget features. This is fine, except for post-ra scheduling. Whether to use the old post-ra list scheduler or the post-ra machine schedule is decided as the pass manager is set up, in arms case from a newly constructed subtarget. Under some situations, like LTO, this won't include the correct cpu so can pick the wrong option. This can have a surprising effect on performance. To fix that, this patch overrides targetSchedulesPostRAScheduling and addPreSched2 in the ARM backend, adding _both_ post-ra schedulers and picking at runtime which to execute. To pick between the two I've had to add a enablePostRAMachineScheduler() method that normally returns enableMachineScheduler() && enablePostRAScheduler(), which can be overridden to enable just one of PostRAMachineScheduler vs PostRAScheduler. Thanks to David Penry for the identifying this problem. Differential Revision: https://reviews.llvm.org/D69775
66 lines
1.9 KiB
C++
66 lines
1.9 KiB
C++
//===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
/// \file This file describes the general parts of a Subtarget.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "llvm/CodeGen/TargetSubtargetInfo.h"
|
|
|
|
using namespace llvm;
|
|
|
|
TargetSubtargetInfo::TargetSubtargetInfo(
|
|
const Triple &TT, StringRef CPU, StringRef FS,
|
|
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD,
|
|
const MCWriteProcResEntry *WPR,
|
|
const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
|
|
const InstrStage *IS, const unsigned *OC, const unsigned *FP)
|
|
: MCSubtargetInfo(TT, CPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {
|
|
}
|
|
|
|
TargetSubtargetInfo::~TargetSubtargetInfo() = default;
|
|
|
|
bool TargetSubtargetInfo::enableAtomicExpand() const {
|
|
return true;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enableIndirectBrExpand() const {
|
|
return false;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enableMachineScheduler() const {
|
|
return false;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
|
|
return enableMachineScheduler();
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enableRALocalReassignment(
|
|
CodeGenOpt::Level OptLevel) const {
|
|
return true;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enableAdvancedRASplitCost() const {
|
|
return false;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enablePostRAScheduler() const {
|
|
return getSchedModel().PostRAScheduler;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enablePostRAMachineScheduler() const {
|
|
return enableMachineScheduler() && enablePostRAScheduler();
|
|
}
|
|
|
|
bool TargetSubtargetInfo::useAA() const {
|
|
return false;
|
|
}
|
|
|
|
void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const { }
|