mirror of
https://github.com/RPCS3/llvm-mirror.git
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d49cb60862
Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
880 lines
31 KiB
C++
880 lines
31 KiB
C++
//===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the class that prints out the LLVM IR and machine
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// functions using the MIR serialization format.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MIRPrinter.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/None.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallBitVector.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/MIRYamlMapping.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DebugInfo.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/IR/IRPrintingPasses.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/Module.h"
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#include "llvm/IR/ModuleSlotTracker.h"
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#include "llvm/IR/Value.h"
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#include "llvm/MC/LaneBitmask.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDwarf.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/AtomicOrdering.h"
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#include "llvm/Support/BranchProbability.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/LowLevelTypeImpl.h"
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#include "llvm/Support/YAMLTraits.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetIntrinsicInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include <algorithm>
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#include <cassert>
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#include <cinttypes>
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#include <cstdint>
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#include <iterator>
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#include <string>
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#include <utility>
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#include <vector>
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using namespace llvm;
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static cl::opt<bool> SimplifyMIR(
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"simplify-mir", cl::Hidden,
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cl::desc("Leave out unnecessary information when printing MIR"));
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namespace {
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/// This structure describes how to print out stack object references.
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struct FrameIndexOperand {
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std::string Name;
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unsigned ID;
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bool IsFixed;
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FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
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: Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
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/// Return an ordinary stack object reference.
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static FrameIndexOperand create(StringRef Name, unsigned ID) {
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return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
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}
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/// Return a fixed stack object reference.
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static FrameIndexOperand createFixed(unsigned ID) {
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return FrameIndexOperand("", ID, /*IsFixed=*/true);
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}
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};
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} // end anonymous namespace
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namespace llvm {
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/// This class prints out the machine functions using the MIR serialization
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/// format.
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class MIRPrinter {
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raw_ostream &OS;
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DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
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/// Maps from stack object indices to operand indices which will be used when
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/// printing frame index machine operands.
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DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
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public:
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MIRPrinter(raw_ostream &OS) : OS(OS) {}
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void print(const MachineFunction &MF);
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void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
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const TargetRegisterInfo *TRI);
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void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
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const MachineFrameInfo &MFI);
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void convert(yaml::MachineFunction &MF,
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const MachineConstantPool &ConstantPool);
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void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
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const MachineJumpTableInfo &JTI);
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void convertStackObjects(yaml::MachineFunction &YMF,
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const MachineFunction &MF, ModuleSlotTracker &MST);
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void convertCallSiteObjects(yaml::MachineFunction &YMF,
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const MachineFunction &MF,
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ModuleSlotTracker &MST);
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private:
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void initRegisterMaskIds(const MachineFunction &MF);
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};
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/// This class prints out the machine instructions using the MIR serialization
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/// format.
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class MIPrinter {
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raw_ostream &OS;
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ModuleSlotTracker &MST;
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const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
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const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
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/// Synchronization scope names registered with LLVMContext.
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SmallVector<StringRef, 8> SSNs;
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bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
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bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
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public:
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MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
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const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
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const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
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: OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
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StackObjectOperandMapping(StackObjectOperandMapping) {}
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void print(const MachineBasicBlock &MBB);
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void print(const MachineInstr &MI);
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void printStackObjectReference(int FrameIndex);
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void print(const MachineInstr &MI, unsigned OpIdx,
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const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
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LLT TypeToPrint, bool PrintDef = true);
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};
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} // end namespace llvm
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namespace llvm {
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namespace yaml {
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/// This struct serializes the LLVM IR module.
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template <> struct BlockScalarTraits<Module> {
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static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
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Mod.print(OS, nullptr);
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}
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static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
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llvm_unreachable("LLVM Module is supposed to be parsed separately");
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return "";
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}
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};
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} // end namespace yaml
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} // end namespace llvm
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static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
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const TargetRegisterInfo *TRI) {
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raw_string_ostream OS(Dest.Value);
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OS << printReg(Reg, TRI);
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}
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void MIRPrinter::print(const MachineFunction &MF) {
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initRegisterMaskIds(MF);
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yaml::MachineFunction YamlMF;
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YamlMF.Name = MF.getName();
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YamlMF.Alignment = MF.getAlignment().value();
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YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
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YamlMF.HasWinCFI = MF.hasWinCFI();
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YamlMF.Legalized = MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::Legalized);
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YamlMF.RegBankSelected = MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::RegBankSelected);
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YamlMF.Selected = MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::Selected);
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YamlMF.FailedISel = MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel);
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convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
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ModuleSlotTracker MST(MF.getFunction().getParent());
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MST.incorporateFunction(MF.getFunction());
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convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
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convertStackObjects(YamlMF, MF, MST);
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convertCallSiteObjects(YamlMF, MF, MST);
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if (const auto *ConstantPool = MF.getConstantPool())
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convert(YamlMF, *ConstantPool);
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if (const auto *JumpTableInfo = MF.getJumpTableInfo())
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convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
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const TargetMachine &TM = MF.getTarget();
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YamlMF.MachineFuncInfo =
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std::unique_ptr<yaml::MachineFunctionInfo>(TM.convertFuncInfoToYAML(MF));
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raw_string_ostream StrOS(YamlMF.Body.Value.Value);
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bool IsNewlineNeeded = false;
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for (const auto &MBB : MF) {
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if (IsNewlineNeeded)
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StrOS << "\n";
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MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
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.print(MBB);
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IsNewlineNeeded = true;
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}
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StrOS.flush();
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yaml::Output Out(OS);
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if (!SimplifyMIR)
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Out.setWriteDefaultValues(true);
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Out << YamlMF;
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}
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static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
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const TargetRegisterInfo *TRI) {
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assert(RegMask && "Can't print an empty register mask");
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OS << StringRef("CustomRegMask(");
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bool IsRegInRegMaskFound = false;
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for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
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// Check whether the register is asserted in regmask.
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if (RegMask[I / 32] & (1u << (I % 32))) {
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if (IsRegInRegMaskFound)
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OS << ',';
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OS << printReg(I, TRI);
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IsRegInRegMaskFound = true;
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}
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}
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OS << ')';
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}
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static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
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const MachineRegisterInfo &RegInfo,
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const TargetRegisterInfo *TRI) {
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raw_string_ostream OS(Dest.Value);
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OS << printRegClassOrBank(Reg, RegInfo, TRI);
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}
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template <typename T>
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static void
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printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
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T &Object, ModuleSlotTracker &MST) {
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std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value,
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&Object.DebugExpr.Value,
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&Object.DebugLoc.Value}};
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std::array<const Metadata *, 3> Metas{{DebugVar.Var,
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DebugVar.Expr,
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DebugVar.Loc}};
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for (unsigned i = 0; i < 3; ++i) {
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raw_string_ostream StrOS(*Outputs[i]);
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Metas[i]->printAsOperand(StrOS, MST);
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}
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}
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void MIRPrinter::convert(yaml::MachineFunction &MF,
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const MachineRegisterInfo &RegInfo,
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const TargetRegisterInfo *TRI) {
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MF.TracksRegLiveness = RegInfo.tracksLiveness();
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// Print the virtual register definitions.
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for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
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unsigned Reg = Register::index2VirtReg(I);
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yaml::VirtualRegisterDefinition VReg;
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VReg.ID = I;
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if (RegInfo.getVRegName(Reg) != "")
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continue;
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::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
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unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
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if (PreferredReg)
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printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
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MF.VirtualRegisters.push_back(VReg);
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}
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// Print the live ins.
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for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
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yaml::MachineFunctionLiveIn LiveIn;
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printRegMIR(LI.first, LiveIn.Register, TRI);
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if (LI.second)
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printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
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MF.LiveIns.push_back(LiveIn);
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}
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// Prints the callee saved registers.
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if (RegInfo.isUpdatedCSRsInitialized()) {
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const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
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std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
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for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
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yaml::FlowStringValue Reg;
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printRegMIR(*I, Reg, TRI);
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CalleeSavedRegisters.push_back(Reg);
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}
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MF.CalleeSavedRegisters = CalleeSavedRegisters;
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}
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}
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void MIRPrinter::convert(ModuleSlotTracker &MST,
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yaml::MachineFrameInfo &YamlMFI,
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const MachineFrameInfo &MFI) {
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YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
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YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
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YamlMFI.HasStackMap = MFI.hasStackMap();
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YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
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YamlMFI.StackSize = MFI.getStackSize();
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YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
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YamlMFI.MaxAlignment = MFI.getMaxAlignment();
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YamlMFI.AdjustsStack = MFI.adjustsStack();
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YamlMFI.HasCalls = MFI.hasCalls();
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YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
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? MFI.getMaxCallFrameSize() : ~0u;
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YamlMFI.CVBytesOfCalleeSavedRegisters =
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MFI.getCVBytesOfCalleeSavedRegisters();
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YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
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YamlMFI.HasVAStart = MFI.hasVAStart();
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YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
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YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
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if (MFI.getSavePoint()) {
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raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
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StrOS << printMBBReference(*MFI.getSavePoint());
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}
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if (MFI.getRestorePoint()) {
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raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
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StrOS << printMBBReference(*MFI.getRestorePoint());
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}
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}
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void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
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const MachineFunction &MF,
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ModuleSlotTracker &MST) {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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// Process fixed stack objects.
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unsigned ID = 0;
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for (int I = MFI.getObjectIndexBegin(); I < 0; ++I, ++ID) {
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if (MFI.isDeadObjectIndex(I))
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continue;
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yaml::FixedMachineStackObject YamlObject;
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YamlObject.ID = ID;
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YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
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? yaml::FixedMachineStackObject::SpillSlot
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: yaml::FixedMachineStackObject::DefaultType;
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YamlObject.Offset = MFI.getObjectOffset(I);
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YamlObject.Size = MFI.getObjectSize(I);
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YamlObject.Alignment = MFI.getObjectAlignment(I);
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YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I);
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YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
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YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
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YMF.FixedStackObjects.push_back(YamlObject);
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StackObjectOperandMapping.insert(
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std::make_pair(I, FrameIndexOperand::createFixed(ID)));
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}
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// Process ordinary stack objects.
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ID = 0;
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for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I, ++ID) {
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if (MFI.isDeadObjectIndex(I))
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continue;
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yaml::MachineStackObject YamlObject;
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YamlObject.ID = ID;
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if (const auto *Alloca = MFI.getObjectAllocation(I))
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YamlObject.Name.Value =
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Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
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YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
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? yaml::MachineStackObject::SpillSlot
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: MFI.isVariableSizedObjectIndex(I)
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? yaml::MachineStackObject::VariableSized
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: yaml::MachineStackObject::DefaultType;
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YamlObject.Offset = MFI.getObjectOffset(I);
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YamlObject.Size = MFI.getObjectSize(I);
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YamlObject.Alignment = MFI.getObjectAlignment(I);
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YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I);
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YMF.StackObjects.push_back(YamlObject);
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StackObjectOperandMapping.insert(std::make_pair(
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I, FrameIndexOperand::create(YamlObject.Name.Value, ID)));
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}
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for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
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if (!CSInfo.isSpilledToReg() && MFI.isDeadObjectIndex(CSInfo.getFrameIdx()))
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continue;
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yaml::StringValue Reg;
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printRegMIR(CSInfo.getReg(), Reg, TRI);
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if (!CSInfo.isSpilledToReg()) {
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auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
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assert(StackObjectInfo != StackObjectOperandMapping.end() &&
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"Invalid stack object index");
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const FrameIndexOperand &StackObject = StackObjectInfo->second;
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if (StackObject.IsFixed) {
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YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
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YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
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CSInfo.isRestored();
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} else {
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YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
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YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
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CSInfo.isRestored();
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}
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}
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}
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for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
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auto LocalObject = MFI.getLocalFrameObjectMap(I);
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auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
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assert(StackObjectInfo != StackObjectOperandMapping.end() &&
|
|
"Invalid stack object index");
|
|
const FrameIndexOperand &StackObject = StackObjectInfo->second;
|
|
assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
|
|
YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
|
|
}
|
|
|
|
// Print the stack object references in the frame information class after
|
|
// converting the stack objects.
|
|
if (MFI.hasStackProtectorIndex()) {
|
|
raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
|
|
MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
|
|
.printStackObjectReference(MFI.getStackProtectorIndex());
|
|
}
|
|
|
|
// Print the debug variable information.
|
|
for (const MachineFunction::VariableDbgInfo &DebugVar :
|
|
MF.getVariableDbgInfo()) {
|
|
auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
|
|
assert(StackObjectInfo != StackObjectOperandMapping.end() &&
|
|
"Invalid stack object index");
|
|
const FrameIndexOperand &StackObject = StackObjectInfo->second;
|
|
if (StackObject.IsFixed) {
|
|
auto &Object = YMF.FixedStackObjects[StackObject.ID];
|
|
printStackObjectDbgInfo(DebugVar, Object, MST);
|
|
} else {
|
|
auto &Object = YMF.StackObjects[StackObject.ID];
|
|
printStackObjectDbgInfo(DebugVar, Object, MST);
|
|
}
|
|
}
|
|
}
|
|
|
|
void MIRPrinter::convertCallSiteObjects(yaml::MachineFunction &YMF,
|
|
const MachineFunction &MF,
|
|
ModuleSlotTracker &MST) {
|
|
const auto *TRI = MF.getSubtarget().getRegisterInfo();
|
|
for (auto CSInfo : MF.getCallSitesInfo()) {
|
|
yaml::CallSiteInfo YmlCS;
|
|
yaml::CallSiteInfo::MachineInstrLoc CallLocation;
|
|
|
|
// Prepare instruction position.
|
|
MachineBasicBlock::const_instr_iterator CallI = CSInfo.first->getIterator();
|
|
CallLocation.BlockNum = CallI->getParent()->getNumber();
|
|
// Get call instruction offset from the beginning of block.
|
|
CallLocation.Offset =
|
|
std::distance(CallI->getParent()->instr_begin(), CallI);
|
|
YmlCS.CallLocation = CallLocation;
|
|
// Construct call arguments and theirs forwarding register info.
|
|
for (auto ArgReg : CSInfo.second) {
|
|
yaml::CallSiteInfo::ArgRegPair YmlArgReg;
|
|
YmlArgReg.ArgNo = ArgReg.ArgNo;
|
|
printRegMIR(ArgReg.Reg, YmlArgReg.Reg, TRI);
|
|
YmlCS.ArgForwardingRegs.emplace_back(YmlArgReg);
|
|
}
|
|
YMF.CallSitesInfo.push_back(YmlCS);
|
|
}
|
|
|
|
// Sort call info by position of call instructions.
|
|
llvm::sort(YMF.CallSitesInfo.begin(), YMF.CallSitesInfo.end(),
|
|
[](yaml::CallSiteInfo A, yaml::CallSiteInfo B) {
|
|
if (A.CallLocation.BlockNum == B.CallLocation.BlockNum)
|
|
return A.CallLocation.Offset < B.CallLocation.Offset;
|
|
return A.CallLocation.BlockNum < B.CallLocation.BlockNum;
|
|
});
|
|
}
|
|
|
|
void MIRPrinter::convert(yaml::MachineFunction &MF,
|
|
const MachineConstantPool &ConstantPool) {
|
|
unsigned ID = 0;
|
|
for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
|
|
std::string Str;
|
|
raw_string_ostream StrOS(Str);
|
|
if (Constant.isMachineConstantPoolEntry()) {
|
|
Constant.Val.MachineCPVal->print(StrOS);
|
|
} else {
|
|
Constant.Val.ConstVal->printAsOperand(StrOS);
|
|
}
|
|
|
|
yaml::MachineConstantPoolValue YamlConstant;
|
|
YamlConstant.ID = ID++;
|
|
YamlConstant.Value = StrOS.str();
|
|
YamlConstant.Alignment = Constant.getAlignment();
|
|
YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
|
|
|
|
MF.Constants.push_back(YamlConstant);
|
|
}
|
|
}
|
|
|
|
void MIRPrinter::convert(ModuleSlotTracker &MST,
|
|
yaml::MachineJumpTable &YamlJTI,
|
|
const MachineJumpTableInfo &JTI) {
|
|
YamlJTI.Kind = JTI.getEntryKind();
|
|
unsigned ID = 0;
|
|
for (const auto &Table : JTI.getJumpTables()) {
|
|
std::string Str;
|
|
yaml::MachineJumpTable::Entry Entry;
|
|
Entry.ID = ID++;
|
|
for (const auto *MBB : Table.MBBs) {
|
|
raw_string_ostream StrOS(Str);
|
|
StrOS << printMBBReference(*MBB);
|
|
Entry.Blocks.push_back(StrOS.str());
|
|
Str.clear();
|
|
}
|
|
YamlJTI.Entries.push_back(Entry);
|
|
}
|
|
}
|
|
|
|
void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
|
|
const auto *TRI = MF.getSubtarget().getRegisterInfo();
|
|
unsigned I = 0;
|
|
for (const uint32_t *Mask : TRI->getRegMasks())
|
|
RegisterMaskIds.insert(std::make_pair(Mask, I++));
|
|
}
|
|
|
|
void llvm::guessSuccessors(const MachineBasicBlock &MBB,
|
|
SmallVectorImpl<MachineBasicBlock*> &Result,
|
|
bool &IsFallthrough) {
|
|
SmallPtrSet<MachineBasicBlock*,8> Seen;
|
|
|
|
for (const MachineInstr &MI : MBB) {
|
|
if (MI.isPHI())
|
|
continue;
|
|
for (const MachineOperand &MO : MI.operands()) {
|
|
if (!MO.isMBB())
|
|
continue;
|
|
MachineBasicBlock *Succ = MO.getMBB();
|
|
auto RP = Seen.insert(Succ);
|
|
if (RP.second)
|
|
Result.push_back(Succ);
|
|
}
|
|
}
|
|
MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
|
|
IsFallthrough = I == MBB.end() || !I->isBarrier();
|
|
}
|
|
|
|
bool
|
|
MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
|
|
if (MBB.succ_size() <= 1)
|
|
return true;
|
|
if (!MBB.hasSuccessorProbabilities())
|
|
return true;
|
|
|
|
SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
|
|
MBB.Probs.end());
|
|
BranchProbability::normalizeProbabilities(Normalized.begin(),
|
|
Normalized.end());
|
|
SmallVector<BranchProbability,8> Equal(Normalized.size());
|
|
BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
|
|
|
|
return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
|
|
}
|
|
|
|
bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
|
|
SmallVector<MachineBasicBlock*,8> GuessedSuccs;
|
|
bool GuessedFallthrough;
|
|
guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
|
|
if (GuessedFallthrough) {
|
|
const MachineFunction &MF = *MBB.getParent();
|
|
MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
|
|
if (NextI != MF.end()) {
|
|
MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
|
|
if (!is_contained(GuessedSuccs, Next))
|
|
GuessedSuccs.push_back(Next);
|
|
}
|
|
}
|
|
if (GuessedSuccs.size() != MBB.succ_size())
|
|
return false;
|
|
return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
|
|
}
|
|
|
|
void MIPrinter::print(const MachineBasicBlock &MBB) {
|
|
assert(MBB.getNumber() >= 0 && "Invalid MBB number");
|
|
OS << "bb." << MBB.getNumber();
|
|
bool HasAttributes = false;
|
|
if (const auto *BB = MBB.getBasicBlock()) {
|
|
if (BB->hasName()) {
|
|
OS << "." << BB->getName();
|
|
} else {
|
|
HasAttributes = true;
|
|
OS << " (";
|
|
int Slot = MST.getLocalSlot(BB);
|
|
if (Slot == -1)
|
|
OS << "<ir-block badref>";
|
|
else
|
|
OS << (Twine("%ir-block.") + Twine(Slot)).str();
|
|
}
|
|
}
|
|
if (MBB.hasAddressTaken()) {
|
|
OS << (HasAttributes ? ", " : " (");
|
|
OS << "address-taken";
|
|
HasAttributes = true;
|
|
}
|
|
if (MBB.isEHPad()) {
|
|
OS << (HasAttributes ? ", " : " (");
|
|
OS << "landing-pad";
|
|
HasAttributes = true;
|
|
}
|
|
if (MBB.getLogAlignment()) {
|
|
OS << (HasAttributes ? ", " : " (");
|
|
OS << "align "
|
|
<< (1UL << MBB.getLogAlignment());
|
|
HasAttributes = true;
|
|
}
|
|
if (HasAttributes)
|
|
OS << ")";
|
|
OS << ":\n";
|
|
|
|
bool HasLineAttributes = false;
|
|
// Print the successors
|
|
bool canPredictProbs = canPredictBranchProbabilities(MBB);
|
|
// Even if the list of successors is empty, if we cannot guess it,
|
|
// we need to print it to tell the parser that the list is empty.
|
|
// This is needed, because MI model unreachable as empty blocks
|
|
// with an empty successor list. If the parser would see that
|
|
// without the successor list, it would guess the code would
|
|
// fallthrough.
|
|
if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
|
|
!canPredictSuccessors(MBB)) {
|
|
OS.indent(2) << "successors: ";
|
|
for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
|
|
if (I != MBB.succ_begin())
|
|
OS << ", ";
|
|
OS << printMBBReference(**I);
|
|
if (!SimplifyMIR || !canPredictProbs)
|
|
OS << '('
|
|
<< format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
|
|
<< ')';
|
|
}
|
|
OS << "\n";
|
|
HasLineAttributes = true;
|
|
}
|
|
|
|
// Print the live in registers.
|
|
const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
|
|
if (MRI.tracksLiveness() && !MBB.livein_empty()) {
|
|
const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
|
|
OS.indent(2) << "liveins: ";
|
|
bool First = true;
|
|
for (const auto &LI : MBB.liveins()) {
|
|
if (!First)
|
|
OS << ", ";
|
|
First = false;
|
|
OS << printReg(LI.PhysReg, &TRI);
|
|
if (!LI.LaneMask.all())
|
|
OS << ":0x" << PrintLaneMask(LI.LaneMask);
|
|
}
|
|
OS << "\n";
|
|
HasLineAttributes = true;
|
|
}
|
|
|
|
if (HasLineAttributes)
|
|
OS << "\n";
|
|
bool IsInBundle = false;
|
|
for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
|
|
const MachineInstr &MI = *I;
|
|
if (IsInBundle && !MI.isInsideBundle()) {
|
|
OS.indent(2) << "}\n";
|
|
IsInBundle = false;
|
|
}
|
|
OS.indent(IsInBundle ? 4 : 2);
|
|
print(MI);
|
|
if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
|
|
OS << " {";
|
|
IsInBundle = true;
|
|
}
|
|
OS << "\n";
|
|
}
|
|
if (IsInBundle)
|
|
OS.indent(2) << "}\n";
|
|
}
|
|
|
|
void MIPrinter::print(const MachineInstr &MI) {
|
|
const auto *MF = MI.getMF();
|
|
const auto &MRI = MF->getRegInfo();
|
|
const auto &SubTarget = MF->getSubtarget();
|
|
const auto *TRI = SubTarget.getRegisterInfo();
|
|
assert(TRI && "Expected target register info");
|
|
const auto *TII = SubTarget.getInstrInfo();
|
|
assert(TII && "Expected target instruction info");
|
|
if (MI.isCFIInstruction())
|
|
assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
|
|
|
|
SmallBitVector PrintedTypes(8);
|
|
bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
|
|
unsigned I = 0, E = MI.getNumOperands();
|
|
for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
|
|
!MI.getOperand(I).isImplicit();
|
|
++I) {
|
|
if (I)
|
|
OS << ", ";
|
|
print(MI, I, TRI, ShouldPrintRegisterTies,
|
|
MI.getTypeToPrint(I, PrintedTypes, MRI),
|
|
/*PrintDef=*/false);
|
|
}
|
|
|
|
if (I)
|
|
OS << " = ";
|
|
if (MI.getFlag(MachineInstr::FrameSetup))
|
|
OS << "frame-setup ";
|
|
if (MI.getFlag(MachineInstr::FrameDestroy))
|
|
OS << "frame-destroy ";
|
|
if (MI.getFlag(MachineInstr::FmNoNans))
|
|
OS << "nnan ";
|
|
if (MI.getFlag(MachineInstr::FmNoInfs))
|
|
OS << "ninf ";
|
|
if (MI.getFlag(MachineInstr::FmNsz))
|
|
OS << "nsz ";
|
|
if (MI.getFlag(MachineInstr::FmArcp))
|
|
OS << "arcp ";
|
|
if (MI.getFlag(MachineInstr::FmContract))
|
|
OS << "contract ";
|
|
if (MI.getFlag(MachineInstr::FmAfn))
|
|
OS << "afn ";
|
|
if (MI.getFlag(MachineInstr::FmReassoc))
|
|
OS << "reassoc ";
|
|
if (MI.getFlag(MachineInstr::NoUWrap))
|
|
OS << "nuw ";
|
|
if (MI.getFlag(MachineInstr::NoSWrap))
|
|
OS << "nsw ";
|
|
if (MI.getFlag(MachineInstr::IsExact))
|
|
OS << "exact ";
|
|
if (MI.getFlag(MachineInstr::FPExcept))
|
|
OS << "fpexcept ";
|
|
|
|
OS << TII->getName(MI.getOpcode());
|
|
if (I < E)
|
|
OS << ' ';
|
|
|
|
bool NeedComma = false;
|
|
for (; I < E; ++I) {
|
|
if (NeedComma)
|
|
OS << ", ";
|
|
print(MI, I, TRI, ShouldPrintRegisterTies,
|
|
MI.getTypeToPrint(I, PrintedTypes, MRI));
|
|
NeedComma = true;
|
|
}
|
|
|
|
// Print any optional symbols attached to this instruction as-if they were
|
|
// operands.
|
|
if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) {
|
|
if (NeedComma)
|
|
OS << ',';
|
|
OS << " pre-instr-symbol ";
|
|
MachineOperand::printSymbol(OS, *PreInstrSymbol);
|
|
NeedComma = true;
|
|
}
|
|
if (MCSymbol *PostInstrSymbol = MI.getPostInstrSymbol()) {
|
|
if (NeedComma)
|
|
OS << ',';
|
|
OS << " post-instr-symbol ";
|
|
MachineOperand::printSymbol(OS, *PostInstrSymbol);
|
|
NeedComma = true;
|
|
}
|
|
|
|
if (const DebugLoc &DL = MI.getDebugLoc()) {
|
|
if (NeedComma)
|
|
OS << ',';
|
|
OS << " debug-location ";
|
|
DL->printAsOperand(OS, MST);
|
|
}
|
|
|
|
if (!MI.memoperands_empty()) {
|
|
OS << " :: ";
|
|
const LLVMContext &Context = MF->getFunction().getContext();
|
|
const MachineFrameInfo &MFI = MF->getFrameInfo();
|
|
bool NeedComma = false;
|
|
for (const auto *Op : MI.memoperands()) {
|
|
if (NeedComma)
|
|
OS << ", ";
|
|
Op->print(OS, MST, SSNs, Context, &MFI, TII);
|
|
NeedComma = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
void MIPrinter::printStackObjectReference(int FrameIndex) {
|
|
auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
|
|
assert(ObjectInfo != StackObjectOperandMapping.end() &&
|
|
"Invalid frame index");
|
|
const FrameIndexOperand &Operand = ObjectInfo->second;
|
|
MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
|
|
Operand.Name);
|
|
}
|
|
|
|
void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
|
|
const TargetRegisterInfo *TRI,
|
|
bool ShouldPrintRegisterTies, LLT TypeToPrint,
|
|
bool PrintDef) {
|
|
const MachineOperand &Op = MI.getOperand(OpIdx);
|
|
switch (Op.getType()) {
|
|
case MachineOperand::MO_Immediate:
|
|
if (MI.isOperandSubregIdx(OpIdx)) {
|
|
MachineOperand::printTargetFlags(OS, Op);
|
|
MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
|
|
break;
|
|
}
|
|
LLVM_FALLTHROUGH;
|
|
case MachineOperand::MO_Register:
|
|
case MachineOperand::MO_CImmediate:
|
|
case MachineOperand::MO_FPImmediate:
|
|
case MachineOperand::MO_MachineBasicBlock:
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
|
case MachineOperand::MO_TargetIndex:
|
|
case MachineOperand::MO_JumpTableIndex:
|
|
case MachineOperand::MO_ExternalSymbol:
|
|
case MachineOperand::MO_GlobalAddress:
|
|
case MachineOperand::MO_RegisterLiveOut:
|
|
case MachineOperand::MO_Metadata:
|
|
case MachineOperand::MO_MCSymbol:
|
|
case MachineOperand::MO_CFIIndex:
|
|
case MachineOperand::MO_IntrinsicID:
|
|
case MachineOperand::MO_Predicate:
|
|
case MachineOperand::MO_BlockAddress:
|
|
case MachineOperand::MO_ShuffleMask: {
|
|
unsigned TiedOperandIdx = 0;
|
|
if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
|
|
TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
|
|
const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
|
|
Op.print(OS, MST, TypeToPrint, PrintDef, /*IsStandalone=*/false,
|
|
ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
|
|
break;
|
|
}
|
|
case MachineOperand::MO_FrameIndex:
|
|
printStackObjectReference(Op.getIndex());
|
|
break;
|
|
case MachineOperand::MO_RegisterMask: {
|
|
auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
|
|
if (RegMaskInfo != RegisterMaskIds.end())
|
|
OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
|
|
else
|
|
printCustomRegMask(Op.getRegMask(), OS, TRI);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
void llvm::printMIR(raw_ostream &OS, const Module &M) {
|
|
yaml::Output Out(OS);
|
|
Out << const_cast<Module &>(M);
|
|
}
|
|
|
|
void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
|
|
MIRPrinter Printer(OS);
|
|
Printer.print(MF);
|
|
}
|