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This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"
For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"
Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.
Differential Revision: https://reviews.llvm.org/D38851
llvm-svn: 316101
80 lines
2.6 KiB
LLVM
80 lines
2.6 KiB
LLVM
; RUN: llc -march=hexagon -filetype=obj -o /dev/null < %s
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; REQUIRES: asserts
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; This crashed in the MC code emitter, because a new-value branch was created
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; with IMPLICIT_DEF as the producer.
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target triple = "hexagon"
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%type.0 = type { %type.1, [64 x i8] }
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%type.1 = type { [12 x i8], %type.2*, double }
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%type.2 = type { i16, i16, [1 x %type.3] }
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%type.3 = type { i32 }
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%type.4 = type { %type.2*, i32 }
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define hidden fastcc i8* @fred(%type.0* nocapture readonly %a0, i8* readonly %a1) unnamed_addr #2 {
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b2:
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%v3 = load i8, i8* %a1, align 1
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br i1 undef, label %b4, label %b24
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b4: ; preds = %b2
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switch i8 %v3, label %b13 [
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i8 25, label %b5
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i8 26, label %b6
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i8 28, label %b8
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i8 27, label %b9
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i8 43, label %b11
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i8 110, label %b12
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]
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b5: ; preds = %b4
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unreachable
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b6: ; preds = %b4
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%v7 = getelementptr inbounds i8, i8* %a1, i32 2
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br label %b16
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b8: ; preds = %b4
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br label %b16
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b9: ; preds = %b4
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%v10 = tail call fastcc i8* @fred(%type.0* undef, i8* undef)
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br label %b24
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b11: ; preds = %b4
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unreachable
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b12: ; preds = %b4
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unreachable
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b13: ; preds = %b4
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br label %b14
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b14: ; preds = %b13
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br i1 undef, label %b15, label %b16
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b15: ; preds = %b14
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unreachable
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b16: ; preds = %b20, %b14, %b8, %b6
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%v17 = phi i8* [ %v21, %b20 ], [ undef, %b14 ], [ undef, %b8 ], [ %v7, %b6 ]
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%v18 = phi i32 [ 0, %b20 ], [ undef, %b14 ], [ 0, %b8 ], [ 8, %b6 ]
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%v19 = icmp sgt i32 %v18, 0
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br i1 %v19, label %b20, label %b24
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b20: ; preds = %b16
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%v21 = getelementptr inbounds i8, i8* %v17, i32 1
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%v22 = load i8, i8* %v17, align 1
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%v23 = icmp eq i8 %v22, undef
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br i1 %v23, label %b16, label %b24
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b24: ; preds = %b20, %b16, %b9, %b2
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%v25 = phi i8* [ null, %b2 ], [ null, %b9 ], [ %v17, %b16 ], [ null, %b20 ]
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ret i8* %v25
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}
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attributes #0 = { argmemonly nounwind }
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attributes #1 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b,-long-calls" }
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attributes #2 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b,-long-calls" }
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