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https://github.com/RPCS3/llvm-mirror.git
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6a55f3d913
Current findBestLoopTop can find and move one kind of block to top, a latch block has one successor. Another common case is:
* a latch block
* it has two successors, one is loop header, another is exit
* it has more than one predecessors
If it is below one of its predecessors P, only P can fall through to it, all other predecessors need a jump to it, and another conditional jump to loop header. If it is moved before loop header, all its predecessors jump to it, then fall through to loop header. So all its predecessors except P can reduce one taken branch.
Differential Revision: https://reviews.llvm.org/D43256
llvm-svn: 363471
81 lines
3.0 KiB
LLVM
81 lines
3.0 KiB
LLVM
; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
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; Rely on the comments generated by llc. Check that "if.then" was not predicated.
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; CHECK: b5
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; CHECK: b2
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; CHECK-NOT: if{{.*}}memd
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%s.0 = type { [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [3 x i32], [24 x i32], [8 x %s.1], [5 x i32] }
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%s.1 = type { i32, i32 }
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@g0 = global i64 0
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@g1 = global i32 0
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@g2 = global i32 0
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@g3 = global i8 0
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declare i32 @llvm.hexagon.S2.cl0(i32) #0
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declare i32 @llvm.hexagon.S2.setbit.r(i32, i32) #0
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declare i64 @llvm.hexagon.M2.vmpy2s.s0(i32, i32) #0
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declare i64 @llvm.hexagon.M2.vmac2s.s0(i64, i32, i32) #0
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declare i64 @llvm.hexagon.A2.vaddws(i64, i64) #0
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declare i64 @llvm.hexagon.A2.vsubws(i64, i64) #0
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declare i32 @llvm.hexagon.A4.modwrapu(i32, i32) #0
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define void @f0(i32 %a0, i64* %a1) #1 {
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b0:
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br label %b1
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b1: ; preds = %b5, %b0
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%v0 = phi i32 [ 0, %b0 ], [ %v26, %b5 ]
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%v1 = phi i32 [ 0, %b0 ], [ %v25, %b5 ]
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%v2 = load i32, i32* @g1, align 4
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%v3 = load i32, i32* @g2, align 8
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%v4 = and i32 %v3, %v2
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br label %b2
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b2: ; preds = %b4, %b1
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%v5 = phi i64 [ %v21, %b4 ], [ 0, %b1 ]
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%v6 = phi i64 [ %v22, %b4 ], [ 0, %b1 ]
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%v7 = phi i32 [ %v9, %b4 ], [ %v4, %b1 ]
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%v8 = tail call i32 @llvm.hexagon.S2.cl0(i32 %v7)
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%v9 = tail call i32 @llvm.hexagon.S2.setbit.r(i32 %v7, i32 %v8)
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%v10 = getelementptr [10 x %s.0], [10 x %s.0]* inttoptr (i32 -121502345 to [10 x %s.0]*), i32 0, i32 %v1
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%v11 = getelementptr %s.0, %s.0* %v10, i32 0, i32 12, i32 %v8
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%v12 = load i32, i32* %v11, align 4
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%v13 = tail call i64 @llvm.hexagon.M2.vmpy2s.s0(i32 %v12, i32 %v12)
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%v14 = getelementptr %s.0, %s.0* %v10, i32 0, i32 13, i32 %v8
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%v15 = load i32, i32* %v14, align 4
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%v16 = tail call i64 @llvm.hexagon.M2.vmac2s.s0(i64 %v13, i32 %v15, i32 %v15)
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%v17 = load i8, i8* @g3, align 1
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%v18 = and i8 %v17, 1
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%v19 = icmp eq i8 %v18, 0
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br i1 %v19, label %b3, label %b4, !prof !0
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b3: ; preds = %b2
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%v20 = tail call i64 @llvm.hexagon.A2.vaddws(i64 %v5, i64 %v16)
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store i64 %v20, i64* %a1, align 8
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br label %b4
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b4: ; preds = %b3, %b2
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%v21 = phi i64 [ %v20, %b3 ], [ %v5, %b2 ]
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%v22 = tail call i64 @llvm.hexagon.A2.vsubws(i64 %v6, i64 %v16)
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%v23 = icmp eq i32 %v9, 0
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br i1 %v23, label %b5, label %b2, !prof !1
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b5: ; preds = %b4
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%v24 = add i32 %v1, 1
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%v25 = tail call i32 @llvm.hexagon.A4.modwrapu(i32 %v24, i32 10) #0
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%v26 = add i32 %v0, 1
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%v27 = icmp eq i32 %v26, %a0
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br i1 %v27, label %b6, label %b1, !prof !1
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b6: ; preds = %b5
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store i64 %v16, i64* @g0, align 8
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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!0 = !{!"branch_weights", i32 99, i32 1}
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!1 = !{!"branch_weights", i32 10, i32 90}
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