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llvm-mirror/test/CodeGen
Jessica Paquette 2dcd508332 [AArch64][GlobalISel] Infer whether G_PHI is going to be a FPR in regbankselect
Some instructions (G_LOAD, G_SELECT, G_UNMERGE_VALUES) check if their uses
will define/use FPRs (using `onlyUsesFP` and `onlyDefinesFP`).

The register bank of a use isn't necessarily known when an instruction asks for
this.

Teach `hasFPConstraints` to look at the instructions feeding into a G_PHI when
its destination bank is unknown. If any of them are FPR, assume the entire
G_PHI will also be assigned a FPR.

Since a phi can have many inputs, and those inputs can in turn be phis,
restrict the search depth to a very low number.

Also improve the docs for `hasFPConstraints` and friends a little.

This is a 0.3% code size improvement on CTMark/Bullet at -O3, and a 0.2% code
size improvement at CTMark/pairlocalalign at -O3.

Differential Revision: https://reviews.llvm.org/D88177
2020-09-28 10:37:09 -07:00
..
AArch64 [AArch64][GlobalISel] Infer whether G_PHI is going to be a FPR in regbankselect 2020-09-28 10:37:09 -07:00
AMDGPU [AMDGPU] Add bfi immediate pattern 2020-09-28 10:16:51 +01:00
ARC
ARM [ARM] Added more patterns to generate SSAT/USAT with shift 2020-09-28 14:50:19 +00:00
AVR
BPF
Generic
Hexagon [Hexagon] Avoid crash on CONCAT_VECTORS with illegal element types 2020-09-24 20:05:23 -05:00
Inputs
Lanai
Mips [CodeGen] Do not call emitGlobalConstantLargeInt for constant requires 8 bytes to store 2020-09-26 08:58:46 +03:00
MIR
MSP430
NVPTX
PowerPC [PowerPC] Clean-up mayRaiseFPException bits 2020-09-28 18:22:12 +08:00
RISCV
SPARC
SystemZ [SystemZ] Optimize bcmp calls (PR47420) 2020-09-25 17:55:39 +02:00
Thumb
Thumb2 [ARM] Added more patterns to generate SSAT/USAT with shift 2020-09-28 14:50:19 +00:00
VE
WebAssembly [WebAssembly] Check features before making SjLj vars thread-local 2020-09-25 11:45:16 -07:00
WinCFGuard
WinEH
X86 [X86] Add some basic i128 udiv test coverage 2020-09-27 16:00:15 +01:00
XCore