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a76ecb87cf
- Add target id support (https://clang.llvm.org/docs/ClangOffloadBundler.html#target-id) - Add code object v4 support (https://llvm.org/docs/AMDGPUUsage.html#elf-code-object) - Add kernarg_size to kernel descriptor - Change trap handler ABI to no longer move queue pointer into s[0:1] - Cleanup ELF definitions - Add V2, V3, V4 suffixes to make a clear distinction for code object version - Consolidate note names Differential Revision: https://reviews.llvm.org/D95638
22 lines
889 B
LLVM
22 lines
889 B
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=HSA %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 < %s | FileCheck --check-prefix=HSA %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 < %s | FileCheck --check-prefix=HSA %s
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declare void @llvm.trap() #0
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declare void @llvm.debugtrap() #1
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; HSA: .amdhsa_kernel trap
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; HSA-NEXT: .amdhsa_group_segment_fixed_size 0
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; HSA-NEXT: .amdhsa_private_segment_fixed_size 0
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; HSA-NEXT: .amdhsa_kernarg_size 8
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; HSA-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
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; HSA: .end_amdhsa_kernel
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define amdgpu_kernel void @trap(i32 addrspace(1)* nocapture readonly %arg0) {
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store volatile i32 1, i32 addrspace(1)* %arg0
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call void @llvm.trap()
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unreachable
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store volatile i32 2, i32 addrspace(1)* %arg0
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ret void
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}
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