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98822b77c0
Summary: We now use a standard fixup type applying the pc-relative address of constant address space variables, and we have the GlobalAddress lowering code add the required 4 byte offset to the global address rather than doing it as part of the fixup. This refactoring will make it easier to use the same code for global address space variables and also simplifies the code. Re-commit this after fixing a bug where we were trying to use a reference to a Triple object that had already been destroyed. Reviewers: arsenm, kzhuravl Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D21154 llvm-svn: 272705
149 lines
5.2 KiB
C++
149 lines
5.2 KiB
C++
//===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
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//
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//===----------------------------------------------------------------------===//
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//
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#include "AMDGPUMCInstLower.h"
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#include "AMDGPUAsmPrinter.h"
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#include "AMDGPUTargetMachine.h"
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#include "InstPrinter/AMDGPUInstPrinter.h"
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#include "R600InstrInfo.h"
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCObjectStreamer.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Format.h"
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#include <algorithm>
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using namespace llvm;
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AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st):
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Ctx(ctx), ST(st)
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{ }
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void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
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int MCOpcode = ST.getInstrInfo()->pseudoToMCOpcode(MI->getOpcode());
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if (MCOpcode == -1) {
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LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
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C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
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"a target-specific version: " + Twine(MI->getOpcode()));
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}
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OutMI.setOpcode(MCOpcode);
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for (const MachineOperand &MO : MI->explicit_operands()) {
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MCOperand MCOp;
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switch (MO.getType()) {
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default:
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llvm_unreachable("unknown operand type");
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::createImm(MO.getImm());
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break;
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case MachineOperand::MO_Register:
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MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
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break;
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case MachineOperand::MO_MachineBasicBlock:
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MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(
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MO.getMBB()->getSymbol(), Ctx));
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break;
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case MachineOperand::MO_GlobalAddress: {
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const GlobalValue *GV = MO.getGlobal();
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MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(GV->getName()));
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const MCExpr *SymExpr = MCSymbolRefExpr::create(Sym, Ctx);
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const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr,
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MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
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MCOp = MCOperand::createExpr(Expr);
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break;
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}
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case MachineOperand::MO_ExternalSymbol: {
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MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
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Sym->setExternal(true);
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const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
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MCOp = MCOperand::createExpr(Expr);
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break;
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}
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}
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OutMI.addOperand(MCOp);
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}
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}
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void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
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AMDGPUMCInstLower MCInstLowering(OutContext, STI);
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StringRef Err;
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if (!STI.getInstrInfo()->verifyInstruction(MI, Err)) {
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LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
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C.emitError("Illegal instruction detected: " + Err);
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MI->dump();
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}
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if (MI->isBundle()) {
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const MachineBasicBlock *MBB = MI->getParent();
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MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
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while (I != MBB->instr_end() && I->isInsideBundle()) {
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EmitInstruction(&*I);
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++I;
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}
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} else {
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MCInst TmpInst;
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MCInstLowering.lower(MI, TmpInst);
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EmitToStreamer(*OutStreamer, TmpInst);
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if (STI.dumpCode()) {
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// Disassemble instruction/operands to text.
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DisasmLines.resize(DisasmLines.size() + 1);
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std::string &DisasmLine = DisasmLines.back();
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raw_string_ostream DisasmStream(DisasmLine);
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AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(),
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*MF->getSubtarget().getInstrInfo(),
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*MF->getSubtarget().getRegisterInfo());
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InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(),
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MF->getSubtarget());
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// Disassemble instruction/operands to hex representation.
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SmallVector<MCFixup, 4> Fixups;
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SmallVector<char, 16> CodeBytes;
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raw_svector_ostream CodeStream(CodeBytes);
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auto &ObjStreamer = static_cast<MCObjectStreamer&>(*OutStreamer);
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MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
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InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups,
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MF->getSubtarget<MCSubtargetInfo>());
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HexLines.resize(HexLines.size() + 1);
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std::string &HexLine = HexLines.back();
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raw_string_ostream HexStream(HexLine);
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for (size_t i = 0; i < CodeBytes.size(); i += 4) {
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unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
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HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
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}
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DisasmStream.flush();
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DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
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}
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}
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}
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