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7d64810efd
The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. llvm-svn: 306514
43 lines
1.5 KiB
LLVM
43 lines
1.5 KiB
LLVM
; RUN: llc -mattr=+fp16 < %s | FileCheck %s
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "armv7a--none-eabi"
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; CHECK-LABEL: test_vec3:
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; CHECK-DAG: vmov.f32 [[SREG1:s[0-9]+]], #1.200000e+01
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; CHECK-DAG: vcvt.f32.s32 [[SREG2:s[0-9]+]],
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; CHECK-DAG: vcvtb.f16.f32 [[SREG3:s[0-9]+]], [[SREG2]]
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; CHECK-DAG: vcvtb.f32.f16 [[SREG4:s[0-9]+]], [[SREG3]]
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; CHECK: vadd.f32 [[SREG5:s[0-9]+]], [[SREG4]], [[SREG1]]
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; CHECK-NEXT: vcvtb.f16.f32 [[SREG6:s[0-9]+]], [[SREG5]]
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; CHECK-NEXT: vmov [[RREG1:r[0-9]+]], [[SREG6]]
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; CHECK-DAG: uxth [[RREG2:r[0-9]+]], [[RREG1]]
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; CHECK-DAG: pkhbt [[RREG3:r[0-9]+]], [[RREG1]], [[RREG1]], lsl #16
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; CHECK-DAG: strh [[RREG1]], [r0, #4]
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; CHECK-DAG: vmov [[DREG:d[0-9]+]], [[RREG3]], [[RREG2]]
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; CHECK-DAG: vst1.32 {[[DREG]][0]}, [r0:32]
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; CHECK-NEXT: bx lr
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define void @test_vec3(<3 x half>* %arr, i32 %i) #0 {
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%H = sitofp i32 %i to half
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%S = fadd half %H, 0xH4A00
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%1 = insertelement <3 x half> undef, half %S, i32 0
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%2 = insertelement <3 x half> %1, half %S, i32 1
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%3 = insertelement <3 x half> %2, half %S, i32 2
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store <3 x half> %3, <3 x half>* %arr, align 8
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ret void
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}
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; CHECK-LABEL: test_bitcast:
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; CHECK: vcvtb.f16.f32
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; CHECK: vcvtb.f16.f32
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; CHECK: vcvtb.f16.f32
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; CHECK: pkhbt
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; CHECK: uxth
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define void @test_bitcast(<3 x half> %inp, <3 x i16>* %arr) #0 {
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%bc = bitcast <3 x half> %inp to <3 x i16>
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store <3 x i16> %bc, <3 x i16>* %arr, align 8
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ret void
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}
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attributes #0 = { nounwind }
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