Ulrich Weigand 85c764c15a [PowerPC] Constrain base register in PPCRegisterInfo::resolveFrameIndex ... I've run into a bug where current LLVM at -O0 (with fast-isel) generated invalid code like: ld 0, 20936(1) # 8-byte Folded Reload stw 12, 10348(0) stw 12, 10344(0) The underlying vreg had been introduced as base register by the Local Stack Slot Allocation pass. That register was constrained to G8RC by PPCRegisterInfo::materializeFrameBaseRegister to match the ADDI instruction used to set it, but it was *not* constrained to G8RC_NOX0 to fit the *use* of the register in an address. That should have happened in PPCRegisterInfo::resolveFrameIndex. This patch adds an appropriate constrainRegClass call. Reviewed by Hal Finkel. llvm-svn: 211897		2014-06-27 13:04:12 +00:00
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AArch64	MachineScheduler: add some book-keeping to fix an assert.	2014-06-27 04:57:05 +00:00
ARM	Fix up scoping in a few tests (and delete one that validates unnecessary behavior).	2014-06-24 20:10:27 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Print a=b as an assignment.	2014-06-24 22:45:16 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Constrain base register in PPCRegisterInfo::resolveFrameIndex	2014-06-27 13:04:12 +00:00
R600	R600: Add some testcases for promote alloca pass.	2014-06-27 03:55:55 +00:00
SPARC
SystemZ
Thumb
Thumb2	ARM: Fix TPsoft for Thumb mode	2014-06-24 15:45:59 +00:00
X86	[x86] Teach the target combine step to aggressively fold pshufd insturcions.	2014-06-27 11:40:13 +00:00
XCore