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3fcc23c823
This adds a generic opcode which communicates that a type has already been
zero-extended from a narrower type.
This is intended to be similar to AssertZext in SelectionDAG.
For example,
```
%x_was_extended:_(s64) = G_ASSERT_ZEXT %x, 16
```
Signifies that the top 48 bits of %x are known to be 0.
This is useful in cases like this:
```
define i1 @zeroext_param(i8 zeroext %x) {
%cmp = icmp ult i8 %x, -20
ret i1 %cmp
}
```
In AArch64, `%x` must use a 32-bit register, which is then truncated to a 8-bit
value.
If we know that `%x` is already zero-ed out in the relevant high bits, we can
avoid the truncate.
Currently, in GISel, this looks like this:
```
_zeroext_param:
and w8, w0, #0xff ; We don't actually need this!
cmp w8, #236
cset w0, lo
ret
```
While SDAG does not produce the truncation, since it knows that it's
unnecessary:
```
_zeroext_param:
cmp w0, #236
cset w0, lo
ret
```
This patch
- Adds G_ASSERT_ZEXT
- Adds MIRBuilder support for it
- Adds MachineVerifier support for it
- Documents it
It also puts G_ASSERT_ZEXT into its own class of "hint instruction." (There
should be a G_ASSERT_SEXT in the future, maybe a G_ASSERT_ALIGN as well.)
This allows us to skip over hints in the legalizer etc. These can then later
be selected like COPY instructions or removed.
Differential Revision: https://reviews.llvm.org/D95564
50 lines
1.7 KiB
C++
50 lines
1.7 KiB
C++
//===-- llvm/CodeGen/TargetOpcodes.h - Target Indep Opcodes -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the target independent instruction opcodes.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_TARGETOPCODES_H
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#define LLVM_CODEGEN_TARGETOPCODES_H
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namespace llvm {
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/// Invariant opcodes: All instruction sets have these as their low opcodes.
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///
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namespace TargetOpcode {
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enum {
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#define HANDLE_TARGET_OPCODE(OPC) OPC,
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#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) IDENT = OPC,
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#include "llvm/Support/TargetOpcodes.def"
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};
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} // end namespace TargetOpcode
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/// Check whether the given Opcode is a generic opcode that is not supposed
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/// to appear after ISel.
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inline bool isPreISelGenericOpcode(unsigned Opcode) {
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return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START &&
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Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END;
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}
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/// Check whether the given Opcode is a target-specific opcode.
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inline bool isTargetSpecificOpcode(unsigned Opcode) {
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return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END;
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}
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/// \returns true if \p Opcode is an optimization hint opcode which is not
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/// supposed to appear after ISel.
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inline bool isPreISelGenericOptimizationHint(unsigned Opcode) {
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return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START &&
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Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END;
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}
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} // end namespace llvm
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#endif
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