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bae1c75f0d
For context, the proposed RISC-V bit manipulation extension has a subset of instructions which require one of two SubtargetFeatures to be enabled, 'zbb' or 'zbp', and there is no defined feature which both of these can imply to use as a constraint either (see comments in D65649). AssemblerPredicates allow multiple SubtargetFeatures to be declared in the "AssemblerCondString" field, separated by commas, and this means that the two features must both be enabled. There is no equivalent to say that _either_ feature X or feature Y must be enabled, short of creating a dummy SubtargetFeature for this purpose and having features X and Y imply the new feature. To solve the case where X or Y is needed without adding a new feature, and to better match a typical TableGen style, this replaces the existing "AssemblerCondString" with a dag "AssemblerCondDag" which represents the same information. Two operators are defined for use with AssemblerCondDag, "all_of", which matches the current behaviour, and "any_of", which adds the new proposed ORing features functionality. This was originally proposed in the RFC at http://lists.llvm.org/pipermail/llvm-dev/2020-February/139138.html Changes to all current backends are mechanical to support the replaced functionality, and are NFCI. At this stage, it is illegal to combine features with ands and ors in a single AssemblerCondDag. I suspect this case is sufficiently rare that adding more complex changes to support it are unnecessary. Differential Revision: https://reviews.llvm.org/D74338
105 lines
4.3 KiB
TableGen
105 lines
4.3 KiB
TableGen
// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | \
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// RUN: FileCheck --check-prefix=DISASS %s
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// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | \
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// RUN: FileCheck --check-prefix=MATCHER %s
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// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | \
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// RUN: FileCheck --check-prefix=WRITER %s
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// Check that combining conditions in AssemblerPredicate generates the correct
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// output when using both the (all_of) AND operator, and the (any_of) OR
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// operator.
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include "llvm/Target/Target.td"
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def archInstrInfo : InstrInfo { }
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def archAsmWriter : AsmWriter {
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int PassSubtarget = 1;
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}
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def arch : Target {
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let InstructionSet = archInstrInfo;
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let AssemblyWriters = [archAsmWriter];
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}
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let Namespace = "arch" in {
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def R0 : Register<"r0">;
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def R1 : Register<"r1">;
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def R2 : Register<"r2">;
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def R3 : Register<"r3">;
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def R4 : Register<"r4">;
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}
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def Regs : RegisterClass<"Regs", [i32], 32, (add R0, R1, R2, R3, R4)>;
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class TestInsn<int Opc, list<Predicate> Preds> : Instruction {
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let Size = 2;
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let OutOperandList = (outs);
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let InOperandList = (ins Regs:$r);
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field bits<16> Inst;
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let Inst = Opc;
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let AsmString = NAME # " $r";
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field bits<16> SoftFail = 0;
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let Predicates = Preds;
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}
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def AsmCond1 : SubtargetFeature<"cond1", "cond1", "true", "">;
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def AsmCond2a: SubtargetFeature<"cond2a", "cond2a", "true", "">;
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def AsmCond2b: SubtargetFeature<"cond2b", "cond2b", "true", "">;
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def AsmCond3a: SubtargetFeature<"cond3a", "cond3a", "true", "">;
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def AsmCond3b: SubtargetFeature<"cond3b", "cond3b", "true", "">;
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def AsmPred1 : Predicate<"Pred1">, AssemblerPredicate<(all_of AsmCond1)>;
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def AsmPred2 : Predicate<"Pred2">, AssemblerPredicate<(all_of AsmCond2a, AsmCond2b)>;
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def AsmPred3 : Predicate<"Pred3">, AssemblerPredicate<(any_of AsmCond3a, AsmCond3b)>;
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// MATCHER: if (FB[arch::AsmCond1])
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// MATCHER-NEXT: Features.set(Feature_AsmPred1Bit);
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// MATCHER-NEXT: if (FB[arch::AsmCond2a] && FB[arch::AsmCond2b])
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// MATCHER-NEXT: Features.set(Feature_AsmPred2Bit);
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// MATCHER-NEXT: if ((FB[arch::AsmCond3a] || FB[arch::AsmCond3b]))
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// MATCHER-NEXT: Features.set(Feature_AsmPred3Bit);
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def insn1 : TestInsn<1, [AsmPred1]>;
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// DISASS: return (Bits[arch::AsmCond1]);
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def insn2 : TestInsn<2, [AsmPred2]>;
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// DISASS: return (Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b])
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def insn3 : TestInsn<3, [AsmPred3]>;
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// DISASS: return ((Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b]))
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def insn4 : TestInsn<4, [AsmPred1, AsmPred2]>;
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// DISASS: return (Bits[arch::AsmCond1] && Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b])
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def insn5 : TestInsn<5, [AsmPred1, AsmPred3]>;
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// DISASS: return (Bits[arch::AsmCond1] && (Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b]))
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def insn6 : TestInsn<6, []>;
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def : InstAlias<"alias1", (insn6 R0)> { let Predicates = [AsmPred1]; }
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// WRITER: // (insn6 R0)
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// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R0},
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// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1},
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def : InstAlias<"alias2", (insn6 R1)> { let Predicates = [AsmPred2]; }
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// WRITER: // (insn6 R1)
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// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R1},
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// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2a},
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// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2b},
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def : InstAlias<"alias3", (insn6 R2)> { let Predicates = [AsmPred3]; }
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// WRITER: // (insn6 R2)
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// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R2},
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// WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3a},
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// WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3b},
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// WRITER-NEXT: {AliasPatternCond::K_EndOrFeatures, 0},
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def : InstAlias<"alias4", (insn6 R3)> { let Predicates = [AsmPred1, AsmPred2]; }
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// WRITER: // (insn6 R3)
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// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R3},
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// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1},
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// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2a},
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// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2b},
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def : InstAlias<"alias5", (insn6 R4)> { let Predicates = [AsmPred1, AsmPred3]; }
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// WRITER: // (insn6 R4)
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// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R4},
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// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1},
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// WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3a},
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// WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3b},
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// WRITER-NEXT: {AliasPatternCond::K_EndOrFeatures, 0},
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