Alex Bradbury 12e6230097 [RISCV] Add support for the various RISC-V FMA instruction variants ...

Adds support for the various RISC-V FMA instructions (fmadd, fmsub, fnmsub, fnmadd).

The criteria for choosing whether a fused add or subtract is used, as well as
whether the product is negated or not, is whether some of the arguments to the
llvm.fma.* intrinsic are negated or not. In the tests, extraneous fadd
instructions were added to avoid the negation being performed using a xor
trick, which prevented the proper FMA forms from being selected and thus
tested.

The FMA instruction patterns might seem incorrect (e.g., fnmadd: -rs1 * rs2 -
rs3), but they should be correct. The misleading names were inherited from
MIPS, where the negation happens after computing the sum.

The llvm.fmuladd.* intrinsics still do not generate RISC-V FMA instructions,
as that depends on TargetLowering::isFMAFasterthanFMulAndFAdd.

Some comments in the test files about what type of instructions are there
tested were updated, to better reflect the current content of those test
files.

Differential Revision: https://reviews.llvm.org/D54205
Patch by Luís Marques.

llvm-svn: 349023

2018-12-13 10:49:05 +00:00

..

AsmParser

[RISCV] Support .option push and .option pop

2018-11-28 16:39:14 +00:00

Disassembler

[RISCV] Support named operands for CSR instructions.

2018-10-04 21:50:54 +00:00

InstPrinter

[RISCV] Fix disassembling of fence instruction with invalid field

2018-10-11 22:49:13 +00:00

MCTargetDesc

[RISCV] Support .option push and .option pop

2018-11-28 16:39:14 +00:00

TargetInfo

Fix RISCV build after r318352

2017-11-16 18:39:31 +00:00

Utils

[RISCV][NFC] Define and use the new CA instruction format

2018-11-16 10:33:23 +00:00

CMakeLists.txt

[RISCV] Support named operands for CSR instructions.

2018-10-04 21:50:54 +00:00

LLVMBuild.txt

[RISCV] Support named operands for CSR instructions.

2018-10-04 21:50:54 +00:00

RISCV.h

[RISCV] Support named operands for CSR instructions.

2018-10-04 21:50:54 +00:00

RISCV.td

[RISCV] Support named operands for CSR instructions.

2018-10-04 21:50:54 +00:00

RISCVAsmPrinter.cpp

Revert "[RISCV] implement li pseudo instruction"

2018-04-18 19:02:31 +00:00

RISCVCallingConv.td

[RISCV] Add support for _interrupt attribute

2018-07-26 17:49:43 +00:00

RISCVExpandPseudoInsts.cpp

[RISCV] Implement codegen for cmpxchg on RV32IA

2018-11-29 20:43:42 +00:00

RISCVFrameLowering.cpp

[RISCV] Fix std::advance slowness

2018-08-24 23:13:59 +00:00

RISCVFrameLowering.h

[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects

2018-03-20 01:39:17 +00:00

RISCVInstrFormats.td

[RISCV][NFC] Define and use the new CA instruction format

2018-11-16 10:33:23 +00:00

RISCVInstrFormatsC.td

[RISCV][NFC] Define and use the new CA instruction format

2018-11-16 10:33:23 +00:00

RISCVInstrInfo.cpp

[RISCV] Remove overzealous is64Bit checks

2018-10-04 14:30:03 +00:00

RISCVInstrInfo.h

[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot

2018-04-26 15:34:27 +00:00

RISCVInstrInfo.td

[RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test cases

2018-12-01 05:00:00 +00:00

RISCVInstrInfoA.td

[RISCV] Implement codegen for cmpxchg on RV32IA

2018-11-29 20:43:42 +00:00

RISCVInstrInfoC.td

[RISCV] Add UNIMP instruction (32- and 16-bit forms)

2018-11-30 13:39:17 +00:00

RISCVInstrInfoD.td

[RISCV] Add support for the various RISC-V FMA instruction variants

2018-12-13 10:49:05 +00:00

RISCVInstrInfoF.td

[RISCV] Add support for the various RISC-V FMA instruction variants

2018-12-13 10:49:05 +00:00

RISCVInstrInfoM.td

[RISCV] Codegen support for the standard RV32M instruction set extension

2018-01-18 12:36:38 +00:00

RISCVISelDAGToDAG.cpp

[RISCV] Introduce codegen patterns for instructions introduced in RV64I

2018-11-30 09:38:44 +00:00

RISCVISelLowering.cpp

[RISCV] Add support for the various RISC-V FMA instruction variants

2018-12-13 10:49:05 +00:00

RISCVISelLowering.h

[TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement for RISC-V

2018-11-30 09:56:54 +00:00

RISCVMachineFunctionInfo.h

[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv

2018-04-12 05:34:25 +00:00

RISCVMCInstLower.cpp

[RISCV] Add codegen for RV32F floating point load/store

2018-03-20 13:26:12 +00:00

RISCVMergeBaseOffset.cpp

Test commit.

2018-08-02 05:38:18 +00:00

RISCVRegisterInfo.cpp

[RISCV] Add support for _interrupt attribute

2018-07-26 17:49:43 +00:00

RISCVRegisterInfo.h

[RISCV] Set isReMaterializable on ADDI and LUI instructions

2018-05-17 15:51:37 +00:00

RISCVRegisterInfo.td

[RISCV] Lower the tail pseudoinstruction

2018-05-23 22:44:08 +00:00

RISCVSubtarget.cpp

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00

RISCVSubtarget.h

[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation

2018-05-15 01:28:50 +00:00

RISCVSystemOperands.td

[RISCV] Support named operands for CSR instructions.

2018-10-04 21:50:54 +00:00

RISCVTargetMachine.cpp

[Targets] Add errors for tiny and kernel codemodel on targets that don't support them

2018-12-07 12:10:23 +00:00

RISCVTargetMachine.h

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00

RISCVTargetObjectFile.cpp

[RISCV] Use init_array instead of ctors for RISCV target, by default

2018-03-24 18:37:19 +00:00

RISCVTargetObjectFile.h

[RISCV] Use init_array instead of ctors for RISCV target, by default

2018-03-24 18:37:19 +00:00