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64f094071b
The uses of CallSite were removed in previous patches.
147 lines
6.0 KiB
C++
147 lines
6.0 KiB
C++
//===- CodeGen/Analysis.h - CodeGen LLVM IR Analysis Utilities --*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares several CodeGen-specific LLVM IR analysis utilities.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_ANALYSIS_H
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#define LLVM_CODEGEN_ANALYSIS_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/Support/CodeGen.h"
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namespace llvm {
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class GlobalValue;
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class LLT;
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class MachineBasicBlock;
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class MachineFunction;
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class TargetLoweringBase;
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class TargetLowering;
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class TargetMachine;
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struct EVT;
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/// Compute the linearized index of a member in a nested
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/// aggregate/struct/array.
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///
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/// Given an LLVM IR aggregate type and a sequence of insertvalue or
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/// extractvalue indices that identify a member, return the linearized index of
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/// the start of the member, i.e the number of element in memory before the
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/// sought one. This is disconnected from the number of bytes.
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///
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/// \param Ty is the type indexed by \p Indices.
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/// \param Indices is an optional pointer in the indices list to the current
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/// index.
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/// \param IndicesEnd is the end of the indices list.
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/// \param CurIndex is the current index in the recursion.
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///
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/// \returns \p CurIndex plus the linear index in \p Ty the indices list.
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unsigned ComputeLinearIndex(Type *Ty,
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const unsigned *Indices,
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const unsigned *IndicesEnd,
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unsigned CurIndex = 0);
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inline unsigned ComputeLinearIndex(Type *Ty,
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ArrayRef<unsigned> Indices,
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unsigned CurIndex = 0) {
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return ComputeLinearIndex(Ty, Indices.begin(), Indices.end(), CurIndex);
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}
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/// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
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/// EVTs that represent all the individual underlying
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/// non-aggregate types that comprise it.
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///
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/// If Offsets is non-null, it points to a vector to be filled in
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/// with the in-memory offsets of each of the individual values.
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///
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void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty,
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SmallVectorImpl<EVT> &ValueVTs,
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SmallVectorImpl<uint64_t> *Offsets = nullptr,
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uint64_t StartingOffset = 0);
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/// Variant of ComputeValueVTs that also produces the memory VTs.
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void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty,
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SmallVectorImpl<EVT> &ValueVTs,
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SmallVectorImpl<EVT> *MemVTs,
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SmallVectorImpl<uint64_t> *Offsets = nullptr,
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uint64_t StartingOffset = 0);
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/// computeValueLLTs - Given an LLVM IR type, compute a sequence of
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/// LLTs that represent all the individual underlying
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/// non-aggregate types that comprise it.
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///
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/// If Offsets is non-null, it points to a vector to be filled in
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/// with the in-memory offsets of each of the individual values.
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///
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void computeValueLLTs(const DataLayout &DL, Type &Ty,
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SmallVectorImpl<LLT> &ValueTys,
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SmallVectorImpl<uint64_t> *Offsets = nullptr,
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uint64_t StartingOffset = 0);
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/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
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GlobalValue *ExtractTypeInfo(Value *V);
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/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
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/// processed uses a memory 'm' constraint.
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bool hasInlineAsmMemConstraint(InlineAsm::ConstraintInfoVector &CInfos,
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const TargetLowering &TLI);
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/// getFCmpCondCode - Return the ISD condition code corresponding to
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/// the given LLVM IR floating-point condition code. This includes
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/// consideration of global floating-point math flags.
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///
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ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
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/// getFCmpCodeWithoutNaN - Given an ISD condition code comparing floats,
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/// return the equivalent code if we're allowed to assume that NaNs won't occur.
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ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
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/// getICmpCondCode - Return the ISD condition code corresponding to
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/// the given LLVM IR integer condition code.
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///
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ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
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/// Test if the given instruction is in a position to be optimized
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/// with a tail-call. This roughly means that it's in a block with
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/// a return and there's nothing that needs to be scheduled
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/// between it and the return.
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///
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/// This function only tests target-independent requirements.
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bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM);
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/// Test if given that the input instruction is in the tail call position, if
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/// there is an attribute mismatch between the caller and the callee that will
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/// inhibit tail call optimizations.
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/// \p AllowDifferingSizes is an output parameter which, if forming a tail call
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/// is permitted, determines whether it's permitted only if the size of the
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/// caller's and callee's return types match exactly.
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bool attributesPermitTailCall(const Function *F, const Instruction *I,
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const ReturnInst *Ret,
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const TargetLoweringBase &TLI,
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bool *AllowDifferingSizes = nullptr);
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/// Test if given that the input instruction is in the tail call position if the
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/// return type or any attributes of the function will inhibit tail call
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/// optimization.
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bool returnTypeIsEligibleForTailCall(const Function *F, const Instruction *I,
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const ReturnInst *Ret,
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const TargetLoweringBase &TLI);
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DenseMap<const MachineBasicBlock *, int>
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getEHScopeMembership(const MachineFunction &MF);
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} // End llvm namespace
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#endif
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