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https://github.com/RPCS3/llvm-mirror.git
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2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
92 lines
2.6 KiB
LLVM
92 lines
2.6 KiB
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
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define <8 x i8> @rbit_8b(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: rbit_8b:
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;CHECK: rbit.8b
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%tmp1 = load <8 x i8>* %A
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%tmp3 = call <8 x i8> @llvm.arm64.neon.rbit.v8i8(<8 x i8> %tmp1)
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ret <8 x i8> %tmp3
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}
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define <16 x i8> @rbit_16b(<16 x i8>* %A) nounwind {
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;CHECK-LABEL: rbit_16b:
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;CHECK: rbit.16b
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%tmp1 = load <16 x i8>* %A
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%tmp3 = call <16 x i8> @llvm.arm64.neon.rbit.v16i8(<16 x i8> %tmp1)
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ret <16 x i8> %tmp3
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}
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declare <8 x i8> @llvm.arm64.neon.rbit.v8i8(<8 x i8>) nounwind readnone
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declare <16 x i8> @llvm.arm64.neon.rbit.v16i8(<16 x i8>) nounwind readnone
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define <8 x i16> @sxtl8h(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: sxtl8h:
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;CHECK: sshll.8h
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%tmp1 = load <8 x i8>* %A
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%tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
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ret <8 x i16> %tmp2
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}
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define <8 x i16> @uxtl8h(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: uxtl8h:
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;CHECK: ushll.8h
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%tmp1 = load <8 x i8>* %A
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%tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @sxtl4s(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: sxtl4s:
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;CHECK: sshll.4s
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%tmp1 = load <4 x i16>* %A
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%tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
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ret <4 x i32> %tmp2
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}
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define <4 x i32> @uxtl4s(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: uxtl4s:
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;CHECK: ushll.4s
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%tmp1 = load <4 x i16>* %A
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%tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @sxtl2d(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: sxtl2d:
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;CHECK: sshll.2d
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%tmp1 = load <2 x i32>* %A
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%tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
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ret <2 x i64> %tmp2
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}
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define <2 x i64> @uxtl2d(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: uxtl2d:
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;CHECK: ushll.2d
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%tmp1 = load <2 x i32>* %A
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%tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
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ret <2 x i64> %tmp2
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}
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; Check for incorrect use of vector bic.
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; rdar://11553859
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define void @test_vsliq(i8* nocapture %src, i8* nocapture %dest) nounwind noinline ssp {
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entry:
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; CHECK-LABEL: test_vsliq:
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; CHECK-NOT: bic
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; CHECK: movi.2d [[REG1:v[0-9]+]], #0x0000ff000000ff
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; CHECK: and.16b v{{[0-9]+}}, v{{[0-9]+}}, [[REG1]]
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%0 = bitcast i8* %src to <16 x i8>*
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%1 = load <16 x i8>* %0, align 16
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%and.i = and <16 x i8> %1, <i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0>
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%2 = bitcast <16 x i8> %and.i to <8 x i16>
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%vshl_n = shl <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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%3 = or <8 x i16> %2, %vshl_n
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%4 = bitcast <8 x i16> %3 to <4 x i32>
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%vshl_n8 = shl <4 x i32> %4, <i32 16, i32 16, i32 16, i32 16>
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%5 = or <4 x i32> %4, %vshl_n8
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%6 = bitcast <4 x i32> %5 to <16 x i8>
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%7 = bitcast i8* %dest to <16 x i8>*
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store <16 x i8> %6, <16 x i8>* %7, align 16
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ret void
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}
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