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270ef28ce9
Replace the UsePostRAScheduler SubtargetFeature with DisablePostRAScheduler, which is then used by Swift and Cyclone. This patch maintains enabling PostRA scheduling for other Thumb2 capable cores and/or for functions which are being compiled in Arm mode. Differential Revision: https://reviews.llvm.org/D37055 llvm-svn: 312226
775 lines
27 KiB
C++
775 lines
27 KiB
C++
//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the ARM specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
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#define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
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#include "ARMBaseInstrInfo.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMConstantPoolValue.h"
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#include "ARMFrameLowering.h"
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#include "ARMISelLowering.h"
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#include "ARMSelectionDAGInfo.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <memory>
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "ARMGenSubtargetInfo.inc"
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namespace llvm {
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class ARMBaseTargetMachine;
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class GlobalValue;
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class StringRef;
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class ARMSubtarget : public ARMGenSubtargetInfo {
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protected:
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enum ARMProcFamilyEnum {
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Others,
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CortexA12,
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CortexA15,
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CortexA17,
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CortexA32,
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CortexA35,
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CortexA5,
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CortexA53,
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CortexA55,
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CortexA57,
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CortexA7,
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CortexA72,
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CortexA73,
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CortexA75,
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CortexA8,
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CortexA9,
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CortexM3,
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CortexR4,
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CortexR4F,
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CortexR5,
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CortexR52,
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CortexR7,
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ExynosM1,
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Krait,
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Kryo,
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Swift
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};
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enum ARMProcClassEnum {
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None,
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AClass,
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MClass,
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RClass
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};
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enum ARMArchEnum {
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ARMv2,
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ARMv2a,
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ARMv3,
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ARMv3m,
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ARMv4,
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ARMv4t,
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ARMv5,
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ARMv5t,
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ARMv5te,
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ARMv5tej,
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ARMv6,
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ARMv6k,
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ARMv6kz,
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ARMv6m,
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ARMv6sm,
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ARMv6t2,
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ARMv7a,
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ARMv7em,
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ARMv7m,
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ARMv7r,
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ARMv7ve,
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ARMv81a,
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ARMv82a,
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ARMv83a,
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ARMv8a,
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ARMv8mBaseline,
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ARMv8mMainline,
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ARMv8r
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};
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public:
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/// What kind of timing do load multiple/store multiple instructions have.
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enum ARMLdStMultipleTiming {
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/// Can load/store 2 registers/cycle.
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DoubleIssue,
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/// Can load/store 2 registers/cycle, but needs an extra cycle if the access
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/// is not 64-bit aligned.
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DoubleIssueCheckUnalignedAccess,
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/// Can load/store 1 register/cycle.
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SingleIssue,
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/// Can load/store 1 register/cycle, but needs an extra cycle for address
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/// computation and potentially also for register writeback.
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SingleIssuePlusExtras,
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};
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protected:
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/// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
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ARMProcFamilyEnum ARMProcFamily = Others;
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/// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
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ARMProcClassEnum ARMProcClass = None;
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/// ARMArch - ARM architecture
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ARMArchEnum ARMArch = ARMv4t;
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/// HasV4TOps, HasV5TOps, HasV5TEOps,
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/// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
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/// Specify whether target support specific ARM ISA variants.
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bool HasV4TOps = false;
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bool HasV5TOps = false;
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bool HasV5TEOps = false;
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bool HasV6Ops = false;
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bool HasV6MOps = false;
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bool HasV6KOps = false;
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bool HasV6T2Ops = false;
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bool HasV7Ops = false;
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bool HasV8Ops = false;
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bool HasV8_1aOps = false;
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bool HasV8_2aOps = false;
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bool HasV8_3aOps = false;
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bool HasV8MBaselineOps = false;
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bool HasV8MMainlineOps = false;
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/// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
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/// floating point ISAs are supported.
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bool HasVFPv2 = false;
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bool HasVFPv3 = false;
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bool HasVFPv4 = false;
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bool HasFPARMv8 = false;
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bool HasNEON = false;
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/// HasDotProd - True if the ARMv8.2A dot product instructions are supported.
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bool HasDotProd = false;
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/// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
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/// specified. Use the method useNEONForSinglePrecisionFP() to
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/// determine if NEON should actually be used.
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bool UseNEONForSinglePrecisionFP = false;
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/// UseMulOps - True if non-microcoded fused integer multiply-add and
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/// multiply-subtract instructions should be used.
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bool UseMulOps = false;
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/// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
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/// whether the FP VML[AS] instructions are slow (if so, don't use them).
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bool SlowFPVMLx = false;
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/// HasVMLxForwarding - If true, NEON has special multiplier accumulator
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/// forwarding to allow mul + mla being issued back to back.
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bool HasVMLxForwarding = false;
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/// SlowFPBrcc - True if floating point compare + branch is slow.
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bool SlowFPBrcc = false;
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/// InThumbMode - True if compiling for Thumb, false for ARM.
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bool InThumbMode = false;
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/// UseSoftFloat - True if we're using software floating point features.
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bool UseSoftFloat = false;
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/// UseMISched - True if MachineScheduler should be used for this subtarget.
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bool UseMISched = false;
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/// DisablePostRAScheduler - False if scheduling should happen again after
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/// register allocation.
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bool DisablePostRAScheduler = false;
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/// HasThumb2 - True if Thumb2 instructions are supported.
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bool HasThumb2 = false;
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/// NoARM - True if subtarget does not support ARM mode execution.
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bool NoARM = false;
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/// ReserveR9 - True if R9 is not available as a general purpose register.
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bool ReserveR9 = false;
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/// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
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/// 32-bit imms (including global addresses).
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bool NoMovt = false;
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/// SupportsTailCall - True if the OS supports tail call. The dynamic linker
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/// must be able to synthesize call stubs for interworking between ARM and
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/// Thumb.
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bool SupportsTailCall = false;
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/// HasFP16 - True if subtarget supports half-precision FP conversions
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bool HasFP16 = false;
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/// HasFullFP16 - True if subtarget supports half-precision FP operations
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bool HasFullFP16 = false;
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/// HasD16 - True if subtarget is limited to 16 double precision
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/// FP registers for VFPv3.
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bool HasD16 = false;
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/// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode
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bool HasHardwareDivideInThumb = false;
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/// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
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bool HasHardwareDivideInARM = false;
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/// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
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/// instructions.
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bool HasDataBarrier = false;
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/// HasV7Clrex - True if the subtarget supports CLREX instructions
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bool HasV7Clrex = false;
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/// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
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/// instructions
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bool HasAcquireRelease = false;
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/// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
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/// over 16-bit ones.
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bool Pref32BitThumb = false;
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/// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
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/// that partially update CPSR and add false dependency on the previous
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/// CPSR setting instruction.
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bool AvoidCPSRPartialUpdate = false;
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/// CheapPredicableCPSRDef - If true, disable +1 predication cost
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/// for instructions updating CPSR. Enabled for Cortex-A57.
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bool CheapPredicableCPSRDef = false;
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/// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
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/// movs with shifter operand (i.e. asr, lsl, lsr).
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bool AvoidMOVsShifterOperand = false;
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/// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
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/// avoid issue "normal" call instructions to callees which do not return.
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bool HasRetAddrStack = false;
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/// HasBranchPredictor - True if the subtarget has a branch predictor. Having
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/// a branch predictor or not changes the expected cost of taking a branch
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/// which affects the choice of whether to use predicated instructions.
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bool HasBranchPredictor = true;
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/// HasMPExtension - True if the subtarget supports Multiprocessing
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/// extension (ARMv7 only).
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bool HasMPExtension = false;
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/// HasVirtualization - True if the subtarget supports the Virtualization
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/// extension.
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bool HasVirtualization = false;
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/// FPOnlySP - If true, the floating point unit only supports single
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/// precision.
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bool FPOnlySP = false;
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/// If true, the processor supports the Performance Monitor Extensions. These
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/// include a generic cycle-counter as well as more fine-grained (often
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/// implementation-specific) events.
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bool HasPerfMon = false;
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/// HasTrustZone - if true, processor supports TrustZone security extensions
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bool HasTrustZone = false;
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/// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
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bool Has8MSecExt = false;
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/// HasCrypto - if true, processor supports Cryptography extensions
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bool HasCrypto = false;
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/// HasCRC - if true, processor supports CRC instructions
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bool HasCRC = false;
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/// HasRAS - if true, the processor supports RAS extensions
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bool HasRAS = false;
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/// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
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/// particularly effective at zeroing a VFP register.
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bool HasZeroCycleZeroing = false;
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/// HasFPAO - if true, processor does positive address offset computation faster
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bool HasFPAO = false;
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/// HasFuseAES - if true, processor executes back to back AES instruction
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/// pairs faster.
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bool HasFuseAES = false;
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/// If true, if conversion may decide to leave some instructions unpredicated.
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bool IsProfitableToUnpredicate = false;
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/// If true, VMOV will be favored over VGETLNi32.
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bool HasSlowVGETLNi32 = false;
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/// If true, VMOV will be favored over VDUP.
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bool HasSlowVDUP32 = false;
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/// If true, VMOVSR will be favored over VMOVDRR.
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bool PreferVMOVSR = false;
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/// If true, ISHST barriers will be used for Release semantics.
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bool PreferISHST = false;
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/// If true, a VLDM/VSTM starting with an odd register number is considered to
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/// take more microops than single VLDRS/VSTRS.
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bool SlowOddRegister = false;
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/// If true, loading into a D subregister will be penalized.
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bool SlowLoadDSubregister = false;
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/// If true, the AGU and NEON/FPU units are multiplexed.
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bool HasMuxedUnits = false;
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/// If true, VMOVS will never be widened to VMOVD
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bool DontWidenVMOVS = false;
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/// If true, run the MLx expansion pass.
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bool ExpandMLx = false;
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/// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
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bool HasVMLxHazards = false;
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// If true, read thread pointer from coprocessor register.
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bool ReadTPHard = false;
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/// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
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bool UseNEONForFPMovs = false;
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/// If true, VLDn instructions take an extra cycle for unaligned accesses.
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bool CheckVLDnAlign = false;
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/// If true, VFP instructions are not pipelined.
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bool NonpipelinedVFP = false;
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/// StrictAlign - If true, the subtarget disallows unaligned memory
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/// accesses for some types. For details, see
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/// ARMTargetLowering::allowsMisalignedMemoryAccesses().
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bool StrictAlign = false;
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/// RestrictIT - If true, the subtarget disallows generation of deprecated IT
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/// blocks to conform to ARMv8 rule.
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bool RestrictIT = false;
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/// HasDSP - If true, the subtarget supports the DSP (saturating arith
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/// and such) instructions.
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bool HasDSP = false;
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/// NaCl TRAP instruction is generated instead of the regular TRAP.
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bool UseNaClTrap = false;
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/// Generate calls via indirect call instructions.
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bool GenLongCalls = false;
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/// Generate code that does not contain data access to code sections.
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bool GenExecuteOnly = false;
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/// Target machine allowed unsafe FP math (such as use of NEON fp)
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bool UnsafeFPMath = false;
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/// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
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bool UseSjLjEH = false;
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/// Implicitly convert an instruction to a different one if its immediates
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/// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
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bool NegativeImmediates = true;
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/// stackAlignment - The minimum alignment known to hold of the stack frame on
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/// entry to the function and which must be maintained by every function.
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unsigned stackAlignment = 4;
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/// CPUString - String name of used CPU.
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std::string CPUString;
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unsigned MaxInterleaveFactor = 1;
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/// Clearance before partial register updates (in number of instructions)
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unsigned PartialUpdateClearance = 0;
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/// What kind of timing do load multiple/store multiple have (double issue,
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/// single issue etc).
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ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue;
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/// The adjustment that we need to apply to get the operand latency from the
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/// operand cycle returned by the itinerary data for pre-ISel operands.
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int PreISelOperandLatencyAdjustment = 2;
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/// IsLittle - The target is Little Endian
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bool IsLittle;
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/// TargetTriple - What processor and OS we're targeting.
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Triple TargetTriple;
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/// SchedModel - Processor specific instruction costs.
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MCSchedModel SchedModel;
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/// Selected instruction itineraries (one entry per itinerary class.)
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InstrItineraryData InstrItins;
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/// Options passed via command line that could influence the target
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const TargetOptions &Options;
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const ARMBaseTargetMachine &TM;
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public:
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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///
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ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
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const ARMBaseTargetMachine &TM, bool IsLittle);
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/// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
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/// that still makes it profitable to inline the call.
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unsigned getMaxInlineSizeThreshold() const {
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return 64;
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}
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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/// initializeSubtargetDependencies - Initializes using a CPU and feature string
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/// so that we can use initializer lists for subtarget initialization.
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ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
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const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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const ARMBaseInstrInfo *getInstrInfo() const override {
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return InstrInfo.get();
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}
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const ARMTargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const ARMFrameLowering *getFrameLowering() const override {
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return FrameLowering.get();
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}
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const ARMBaseRegisterInfo *getRegisterInfo() const override {
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return &InstrInfo->getRegisterInfo();
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}
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const CallLowering *getCallLowering() const override;
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const InstructionSelector *getInstructionSelector() const override;
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const LegalizerInfo *getLegalizerInfo() const override;
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const RegisterBankInfo *getRegBankInfo() const override;
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private:
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ARMSelectionDAGInfo TSInfo;
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// Either Thumb1FrameLowering or ARMFrameLowering.
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std::unique_ptr<ARMFrameLowering> FrameLowering;
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// Either Thumb1InstrInfo or Thumb2InstrInfo.
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std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
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ARMTargetLowering TLInfo;
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/// GlobalISel related APIs.
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std::unique_ptr<CallLowering> CallLoweringInfo;
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std::unique_ptr<InstructionSelector> InstSelector;
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std::unique_ptr<LegalizerInfo> Legalizer;
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std::unique_ptr<RegisterBankInfo> RegBankInfo;
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void initializeEnvironment();
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void initSubtargetFeatures(StringRef CPU, StringRef FS);
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ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
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public:
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void computeIssueWidth();
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bool hasV4TOps() const { return HasV4TOps; }
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bool hasV5TOps() const { return HasV5TOps; }
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bool hasV5TEOps() const { return HasV5TEOps; }
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bool hasV6Ops() const { return HasV6Ops; }
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bool hasV6MOps() const { return HasV6MOps; }
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bool hasV6KOps() const { return HasV6KOps; }
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bool hasV6T2Ops() const { return HasV6T2Ops; }
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bool hasV7Ops() const { return HasV7Ops; }
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bool hasV8Ops() const { return HasV8Ops; }
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bool hasV8_1aOps() const { return HasV8_1aOps; }
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bool hasV8_2aOps() const { return HasV8_2aOps; }
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bool hasV8_3aOps() const { return HasV8_3aOps; }
|
|
bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
|
|
bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
|
|
|
|
/// @{
|
|
/// These functions are obsolete, please consider adding subtarget features
|
|
/// or properties instead of calling them.
|
|
bool isCortexA5() const { return ARMProcFamily == CortexA5; }
|
|
bool isCortexA7() const { return ARMProcFamily == CortexA7; }
|
|
bool isCortexA8() const { return ARMProcFamily == CortexA8; }
|
|
bool isCortexA9() const { return ARMProcFamily == CortexA9; }
|
|
bool isCortexA15() const { return ARMProcFamily == CortexA15; }
|
|
bool isSwift() const { return ARMProcFamily == Swift; }
|
|
bool isCortexM3() const { return ARMProcFamily == CortexM3; }
|
|
bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
|
|
bool isCortexR5() const { return ARMProcFamily == CortexR5; }
|
|
bool isKrait() const { return ARMProcFamily == Krait; }
|
|
/// @}
|
|
|
|
bool hasARMOps() const { return !NoARM; }
|
|
|
|
bool hasVFP2() const { return HasVFPv2; }
|
|
bool hasVFP3() const { return HasVFPv3; }
|
|
bool hasVFP4() const { return HasVFPv4; }
|
|
bool hasFPARMv8() const { return HasFPARMv8; }
|
|
bool hasNEON() const { return HasNEON; }
|
|
bool hasCrypto() const { return HasCrypto; }
|
|
bool hasDotProd() const { return HasDotProd; }
|
|
bool hasCRC() const { return HasCRC; }
|
|
bool hasRAS() const { return HasRAS; }
|
|
bool hasVirtualization() const { return HasVirtualization; }
|
|
|
|
bool useNEONForSinglePrecisionFP() const {
|
|
return hasNEON() && UseNEONForSinglePrecisionFP;
|
|
}
|
|
|
|
bool hasDivideInThumbMode() const { return HasHardwareDivideInThumb; }
|
|
bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
|
|
bool hasDataBarrier() const { return HasDataBarrier; }
|
|
bool hasV7Clrex() const { return HasV7Clrex; }
|
|
bool hasAcquireRelease() const { return HasAcquireRelease; }
|
|
|
|
bool hasAnyDataBarrier() const {
|
|
return HasDataBarrier || (hasV6Ops() && !isThumb());
|
|
}
|
|
|
|
bool useMulOps() const { return UseMulOps; }
|
|
bool useFPVMLx() const { return !SlowFPVMLx; }
|
|
bool hasVMLxForwarding() const { return HasVMLxForwarding; }
|
|
bool isFPBrccSlow() const { return SlowFPBrcc; }
|
|
bool isFPOnlySP() const { return FPOnlySP; }
|
|
bool hasPerfMon() const { return HasPerfMon; }
|
|
bool hasTrustZone() const { return HasTrustZone; }
|
|
bool has8MSecExt() const { return Has8MSecExt; }
|
|
bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
|
|
bool hasFPAO() const { return HasFPAO; }
|
|
bool isProfitableToUnpredicate() const { return IsProfitableToUnpredicate; }
|
|
bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
|
|
bool hasSlowVDUP32() const { return HasSlowVDUP32; }
|
|
bool preferVMOVSR() const { return PreferVMOVSR; }
|
|
bool preferISHSTBarriers() const { return PreferISHST; }
|
|
bool expandMLx() const { return ExpandMLx; }
|
|
bool hasVMLxHazards() const { return HasVMLxHazards; }
|
|
bool hasSlowOddRegister() const { return SlowOddRegister; }
|
|
bool hasSlowLoadDSubregister() const { return SlowLoadDSubregister; }
|
|
bool hasMuxedUnits() const { return HasMuxedUnits; }
|
|
bool dontWidenVMOVS() const { return DontWidenVMOVS; }
|
|
bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
|
|
bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
|
|
bool nonpipelinedVFP() const { return NonpipelinedVFP; }
|
|
bool prefers32BitThumb() const { return Pref32BitThumb; }
|
|
bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
|
|
bool cheapPredicableCPSRDef() const { return CheapPredicableCPSRDef; }
|
|
bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
|
|
bool hasRetAddrStack() const { return HasRetAddrStack; }
|
|
bool hasBranchPredictor() const { return HasBranchPredictor; }
|
|
bool hasMPExtension() const { return HasMPExtension; }
|
|
bool hasDSP() const { return HasDSP; }
|
|
bool useNaClTrap() const { return UseNaClTrap; }
|
|
bool useSjLjEH() const { return UseSjLjEH; }
|
|
bool genLongCalls() const { return GenLongCalls; }
|
|
bool genExecuteOnly() const { return GenExecuteOnly; }
|
|
|
|
bool hasFP16() const { return HasFP16; }
|
|
bool hasD16() const { return HasD16; }
|
|
bool hasFullFP16() const { return HasFullFP16; }
|
|
|
|
bool hasFuseAES() const { return HasFuseAES; }
|
|
/// \brief Return true if the CPU supports any kind of instruction fusion.
|
|
bool hasFusion() const { return hasFuseAES(); }
|
|
|
|
const Triple &getTargetTriple() const { return TargetTriple; }
|
|
|
|
bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
|
|
bool isTargetIOS() const { return TargetTriple.isiOS(); }
|
|
bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
|
|
bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
|
|
bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
|
|
bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
|
|
bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
|
|
bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
|
|
|
|
bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
|
|
bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
|
|
bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
|
|
|
|
// ARM EABI is the bare-metal EABI described in ARM ABI documents and
|
|
// can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
|
|
// FIXME: Add a flag for bare-metal for that target and set Triple::EABI
|
|
// even for GNUEABI, so we can make a distinction here and still conform to
|
|
// the EABI on GNU (and Android) mode. This requires change in Clang, too.
|
|
// FIXME: The Darwin exception is temporary, while we move users to
|
|
// "*-*-*-macho" triples as quickly as possible.
|
|
bool isTargetAEABI() const {
|
|
return (TargetTriple.getEnvironment() == Triple::EABI ||
|
|
TargetTriple.getEnvironment() == Triple::EABIHF) &&
|
|
!isTargetDarwin() && !isTargetWindows();
|
|
}
|
|
bool isTargetGNUAEABI() const {
|
|
return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
|
|
TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
|
|
!isTargetDarwin() && !isTargetWindows();
|
|
}
|
|
bool isTargetMuslAEABI() const {
|
|
return (TargetTriple.getEnvironment() == Triple::MuslEABI ||
|
|
TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
|
|
!isTargetDarwin() && !isTargetWindows();
|
|
}
|
|
|
|
// ARM Targets that support EHABI exception handling standard
|
|
// Darwin uses SjLj. Other targets might need more checks.
|
|
bool isTargetEHABICompatible() const {
|
|
return (TargetTriple.getEnvironment() == Triple::EABI ||
|
|
TargetTriple.getEnvironment() == Triple::GNUEABI ||
|
|
TargetTriple.getEnvironment() == Triple::MuslEABI ||
|
|
TargetTriple.getEnvironment() == Triple::EABIHF ||
|
|
TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
|
|
TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
|
|
isTargetAndroid()) &&
|
|
!isTargetDarwin() && !isTargetWindows();
|
|
}
|
|
|
|
bool isTargetHardFloat() const {
|
|
// FIXME: this is invalid for WindowsCE
|
|
return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
|
|
TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
|
|
TargetTriple.getEnvironment() == Triple::EABIHF ||
|
|
isTargetWindows() || isAAPCS16_ABI();
|
|
}
|
|
|
|
bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
|
|
|
|
bool isXRaySupported() const override;
|
|
|
|
bool isAPCS_ABI() const;
|
|
bool isAAPCS_ABI() const;
|
|
bool isAAPCS16_ABI() const;
|
|
|
|
bool isROPI() const;
|
|
bool isRWPI() const;
|
|
|
|
bool useMachineScheduler() const { return UseMISched; }
|
|
bool disablePostRAScheduler() const { return DisablePostRAScheduler; }
|
|
bool useSoftFloat() const { return UseSoftFloat; }
|
|
bool isThumb() const { return InThumbMode; }
|
|
bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
|
|
bool isThumb2() const { return InThumbMode && HasThumb2; }
|
|
bool hasThumb2() const { return HasThumb2; }
|
|
bool isMClass() const { return ARMProcClass == MClass; }
|
|
bool isRClass() const { return ARMProcClass == RClass; }
|
|
bool isAClass() const { return ARMProcClass == AClass; }
|
|
bool isReadTPHard() const { return ReadTPHard; }
|
|
|
|
bool isR9Reserved() const {
|
|
return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
|
|
}
|
|
|
|
bool useR7AsFramePointer() const {
|
|
return isTargetDarwin() || (!isTargetWindows() && isThumb());
|
|
}
|
|
|
|
/// Returns true if the frame setup is split into two separate pushes (first
|
|
/// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
|
|
/// to lr. This is always required on Thumb1-only targets, as the push and
|
|
/// pop instructions can't access the high registers.
|
|
bool splitFramePushPop(const MachineFunction &MF) const {
|
|
return (useR7AsFramePointer() &&
|
|
MF.getTarget().Options.DisableFramePointerElim(MF)) ||
|
|
isThumb1Only();
|
|
}
|
|
|
|
bool useStride4VFPs(const MachineFunction &MF) const;
|
|
|
|
bool useMovt(const MachineFunction &MF) const;
|
|
|
|
bool supportsTailCall() const { return SupportsTailCall; }
|
|
|
|
bool allowsUnalignedMem() const { return !StrictAlign; }
|
|
|
|
bool restrictIT() const { return RestrictIT; }
|
|
|
|
const std::string & getCPUString() const { return CPUString; }
|
|
|
|
bool isLittle() const { return IsLittle; }
|
|
|
|
unsigned getMispredictionPenalty() const;
|
|
|
|
/// This function returns true if the target has sincos() routine in its
|
|
/// compiler runtime or math libraries.
|
|
bool hasSinCos() const;
|
|
|
|
/// Returns true if machine scheduler should be enabled.
|
|
bool enableMachineScheduler() const override;
|
|
|
|
/// True for some subtargets at > -O0.
|
|
bool enablePostRAScheduler() const override;
|
|
|
|
// enableAtomicExpand- True if we need to expand our atomics.
|
|
bool enableAtomicExpand() const override;
|
|
|
|
/// getInstrItins - Return the instruction itineraries based on subtarget
|
|
/// selection.
|
|
const InstrItineraryData *getInstrItineraryData() const override {
|
|
return &InstrItins;
|
|
}
|
|
|
|
/// getStackAlignment - Returns the minimum alignment known to hold of the
|
|
/// stack frame on entry to the function and which must be maintained by every
|
|
/// function for this subtarget.
|
|
unsigned getStackAlignment() const { return stackAlignment; }
|
|
|
|
unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
|
|
|
|
unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; }
|
|
|
|
ARMLdStMultipleTiming getLdStMultipleTiming() const {
|
|
return LdStMultipleTiming;
|
|
}
|
|
|
|
int getPreISelOperandLatencyAdjustment() const {
|
|
return PreISelOperandLatencyAdjustment;
|
|
}
|
|
|
|
/// True if the GV will be accessed via an indirect symbol.
|
|
bool isGVIndirectSymbol(const GlobalValue *GV) const;
|
|
|
|
/// Returns the constant pool modifier needed to access the GV.
|
|
ARMCP::ARMCPModifier getCPModifier(const GlobalValue *GV) const;
|
|
|
|
/// True if fast-isel is used.
|
|
bool useFastISel() const;
|
|
|
|
/// Returns the correct return opcode for the current feature set.
|
|
/// Use BX if available to allow mixing thumb/arm code, but fall back
|
|
/// to plain mov pc,lr on ARMv4.
|
|
unsigned getReturnOpcode() const {
|
|
if (isThumb())
|
|
return ARM::tBX_RET;
|
|
if (hasV4TOps())
|
|
return ARM::BX_RET;
|
|
return ARM::MOVPCLR;
|
|
}
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
|