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e0801b07e0
target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. llvm-svn: 133782
26 lines
813 B
Makefile
26 lines
813 B
Makefile
##===- lib/Target/XCore/Makefile ---------------------------*- Makefile -*-===##
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#
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# The LLVM Compiler Infrastructure
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#
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# This file is distributed under the University of Illinois Open Source
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# License. See LICENSE.TXT for details.
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#
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##===----------------------------------------------------------------------===##
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LEVEL = ../../..
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LIBRARYNAME = LLVMXCoreCodeGen
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TARGET = XCore
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = XCoreGenRegisterInfo.h.inc XCoreGenRegisterNames.inc \
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XCoreGenRegisterInfo.inc XCoreGenRegisterDesc.inc \
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XCoreGenInstrNames.inc \
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XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \
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XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
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XCoreGenSubtarget.inc
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DIRS = TargetInfo
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include $(LEVEL)/Makefile.common
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