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f5b42453e4
This patch adds instruction selection patterns for the TT, TTT, TTA, and TTAT instructions and tests for llvm.arm.cmse.tt, llvm.arm.cmse.ttt, llvm.arm.cmse.tta, and llvm.arm.cmse.ttat intrinsics (added in a previous patch). Patch by Javed Absar. Differential Revision: https://reviews.llvm.org/D70407
46 lines
1.1 KiB
LLVM
46 lines
1.1 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv8m.base | FileCheck %s
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; RUN: llc < %s -mtriple=thumbebv8m.base | FileCheck %s
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define i32 @test_tt(i8* readnone %p) #0 {
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entry:
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%0 = tail call i32 @llvm.arm.cmse.tt(i8* %p)
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ret i32 %0
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}
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; CHECK-LABEL: test_tt:
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; CHECK: tt r{{[0-9]+}}, r{{[0-9]+}}
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declare i32 @llvm.arm.cmse.tt(i8*) #1
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define i32 @test_ttt(i8* readnone %p) #0 {
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entry:
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%0 = tail call i32 @llvm.arm.cmse.ttt(i8* %p)
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ret i32 %0
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}
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; CHECK-LABEL: test_ttt:
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; CHECK: ttt r{{[0-9]+}}, r{{[0-9]+}}
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declare i32 @llvm.arm.cmse.ttt(i8*) #1
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define i32 @test_tta(i8* readnone %p) #0 {
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entry:
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%0 = tail call i32 @llvm.arm.cmse.tta(i8* %p)
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ret i32 %0
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}
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; CHECK-LABEL: test_tta:
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; CHECK: tta r{{[0-9]+}}, r{{[0-9]+}}
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declare i32 @llvm.arm.cmse.tta(i8*) #1
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define i32 @test_ttat(i8* readnone %p) #0 {
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entry:
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%0 = tail call i32 @llvm.arm.cmse.ttat(i8* %p)
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ret i32 %0
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}
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; CHECK-LABEL: test_ttat:
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; CHECK: ttat r{{[0-9]+}}, r{{[0-9]+}}
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declare i32 @llvm.arm.cmse.ttat(i8*) #1
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attributes #0 = { nounwind readnone "target-features"="+8msecext"}
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attributes #1 = { nounwind readnone }
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