Sander de Smalen 2fbefa55ad [AArch64][SVE] Asm: Support for FMUL (indexed) ... Unpredicated FP-multiply of SVE vector with a vector-element given by vector[index], for example: fmul z0.s, z1.s, z2.s[0] which performs an unpredicated FP-multiply of all 32-bit elements in 'z1' with the first element from 'z2'. This patch adds restricted register classes for SVE vectors: ZPR_3b (only z0..z7 are allowed) - for indexed vector of 16/32-bit elements. ZPR_4b (only z0..z15 are allowed) - for indexed vector of 64-bit elements. Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D48823 llvm-svn: 336205		2018-07-03 15:31:04 +00:00
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AArch64	[AArch64][SVE] Asm: Support for FMUL (indexed)	2018-07-03 15:31:04 +00:00
AMDGPU	[AMDGPU] Fix lit failures introduced in r335281	2018-06-21 22:30:09 +00:00
ARM	[ARM] Add missing Thumb2 assembler diagnostics.	2018-06-28 19:53:12 +00:00
AsmParser	[X86] Fix test/MC/AsmParser/exprs-invalid.s after rL336104	2018-07-02 14:13:27 +00:00
AVR
BPF
COFF
Disassembler	[AArch64] Armv8.4-A: system registers	2018-07-03 12:09:20 +00:00
ELF	Replace unused output filenames with /dev/null in tests	2018-07-02 18:16:44 +00:00
Hexagon	[Hexagon] Fix the value of HexagonII::TypeCVI_FIRST	2018-06-19 18:09:54 +00:00
Lanai
MachO	[MC] Error on a .zerofill directive in a non-virtual section	2018-07-02 17:29:43 +00:00
Mips	[mips] Correct predicates for loads, bit manipulation instructions and some pseudos	2018-06-20 19:59:58 +00:00
PowerPC	[PowerPC] Fix incorrectly encoded wait instruction	2018-06-25 19:28:27 +00:00
RISCV	[RISCV] Tail calls don't need to save return address	2018-06-21 14:37:09 +00:00
Sparc	[Sparc] Add support for 13-bit PIC	2018-06-11 05:50:08 +00:00
SystemZ
WebAssembly	[WebAssembly] Ignore explicit section names for functions	2018-06-14 18:48:19 +00:00
X86	Move REQUIRES: line to the top	2018-06-26 17:44:23 +00:00