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2fc342e80e
The tale starts with r212808 which attempted to fix inversion of the low and high bits when lowering MUL_LOHI. Sadly, that commit did not include any positive test cases, and just removed some operations from a test case where the actual logic being changed isn't fully visible from the test. What this commit did was two things. First, it reversed the low and high results in the formation of the MERGE_VALUES node for the multiple results. This is entirely correct. Second it changed the shuffles for extracting the low and high components from the i64 results of the multiplies to extract them assuming a big-endian-style encoding of the multiply results. This second change is wrong. There is no big-endian encoding in x86, the results of the multiplies are normal v2i64s: when cast to v4i32, the low i32s are at offsets 0 and 2, and the high i32s are at offsets 1 and 3. However, the first change wasn't enough to actually fix the bug, which is (I assume) why the second change was also made. There was another bug in the MERGE_VALUES formation: we weren't using a VTList, and so were getting a single result node! When grabbing the *second* result from the node, we got... well.. colud be anything. I think this *appeared* to invert things, but had to be causing other problems as well. Fortunately, I fixed the MERGE_VALUES issue in r213931, so we should have been fine, right? NOOOPE! Because the core bug was never addressed, the test in vector-idiv failed when I fixed the MERGE_VALUES node. Because there are essentially no docs for this node, I had to guess at how to fix it and tried swapping the operands, restoring the order of the original code before r212808. While this "fixed" the test case (in that we produced the write instructions) we were still extracting the wrong elements of the i64s, and thus PR20355 was still broken. This commit essentially reverts the big-endian-style extraction part of r212808 and goes back to the original masks which were correct. Now that the MERGE_VALUES node formation is also correct, everything works. I've also included a more detailed test from PR20355 to make sure this stays fixed. llvm-svn: 214011
262 lines
6.0 KiB
LLVM
262 lines
6.0 KiB
LLVM
; RUN: llc -march=x86-64 -mcpu=core2 -mattr=+sse4.1 < %s | FileCheck %s -check-prefix=SSE41
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; RUN: llc -march=x86-64 -mcpu=core2 < %s | FileCheck %s -check-prefix=SSE
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; RUN: llc -march=x86-64 -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX
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define <4 x i32> @test1(<4 x i32> %a) {
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%div = udiv <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>
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ret <4 x i32> %div
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; SSE41-LABEL: test1:
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; SSE41: pmuludq
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; SSE41: pshufd $49
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; SSE41: pmuludq
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; SSE41: shufps $-35
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; SSE41: psubd
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; SSE41: psrld $1
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; SSE41: padd
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; SSE41: psrld $2
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; AVX-LABEL: test1:
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; AVX: vpmuludq
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; AVX: vpshufd $49
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; AVX: vpmuludq
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; AVX: vshufps $-35
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; AVX: vpsubd
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; AVX: vpsrld $1
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; AVX: vpadd
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; AVX: vpsrld $2
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}
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define <8 x i32> @test2(<8 x i32> %a) {
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%div = udiv <8 x i32> %a, <i32 7, i32 7, i32 7, i32 7,i32 7, i32 7, i32 7, i32 7>
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ret <8 x i32> %div
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; AVX-LABEL: test2:
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; AVX: vpbroadcastd
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; AVX: vpalignr $4
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; AVX: vpmuludq
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; AVX: vpmuludq
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; AVX: vpblendd $170
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; AVX: vpsubd
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; AVX: vpsrld $1
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; AVX: vpadd
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; AVX: vpsrld $2
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}
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define <8 x i16> @test3(<8 x i16> %a) {
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%div = udiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <8 x i16> %div
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; SSE41-LABEL: test3:
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; SSE41: pmulhuw
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; SSE41: psubw
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; SSE41: psrlw $1
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; SSE41: paddw
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; SSE41: psrlw $2
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; AVX-LABEL: test3:
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; AVX: vpmulhuw
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; AVX: vpsubw
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; AVX: vpsrlw $1
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; AVX: vpaddw
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; AVX: vpsrlw $2
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}
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define <16 x i16> @test4(<16 x i16> %a) {
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%div = udiv <16 x i16> %a, <i16 7, i16 7, i16 7, i16 7,i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7,i16 7, i16 7, i16 7, i16 7>
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ret <16 x i16> %div
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; AVX-LABEL: test4:
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; AVX: vpmulhuw
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; AVX: vpsubw
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; AVX: vpsrlw $1
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; AVX: vpaddw
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; AVX: vpsrlw $2
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; AVX-NOT: vpmulhuw
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}
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define <8 x i16> @test5(<8 x i16> %a) {
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%div = sdiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <8 x i16> %div
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; SSE41-LABEL: test5:
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; SSE41: pmulhw
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; SSE41: psrlw $15
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; SSE41: psraw $1
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; SSE41: paddw
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; AVX-LABEL: test5:
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; AVX: vpmulhw
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; AVX: vpsrlw $15
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; AVX: vpsraw $1
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; AVX: vpaddw
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}
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define <16 x i16> @test6(<16 x i16> %a) {
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%div = sdiv <16 x i16> %a, <i16 7, i16 7, i16 7, i16 7,i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7,i16 7, i16 7, i16 7, i16 7>
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ret <16 x i16> %div
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; AVX-LABEL: test6:
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; AVX: vpmulhw
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; AVX: vpsrlw $15
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; AVX: vpsraw $1
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; AVX: vpaddw
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; AVX-NOT: vpmulhw
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}
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define <16 x i8> @test7(<16 x i8> %a) {
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%div = sdiv <16 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
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ret <16 x i8> %div
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; FIXME: scalarized
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; SSE41-LABEL: test7:
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; SSE41: pext
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; AVX-LABEL: test7:
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; AVX: pext
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}
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define <4 x i32> @test8(<4 x i32> %a) {
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%div = sdiv <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>
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ret <4 x i32> %div
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; SSE41-LABEL: test8:
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; SSE41: pmuldq
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; SSE41: pshufd $49
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; SSE41: pshufd $49
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; SSE41: pmuldq
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; SSE41: shufps $-35
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; SSE41: pshufd $-40
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; SSE41: padd
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; SSE41: psrld $31
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; SSE41: psrad $2
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; SSE41: padd
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; SSE-LABEL: test8:
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; SSE: pmuludq
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; SSE: pshufd $49
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; SSE: pshufd $49
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; SSE: pmuludq
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; SSE: shufps $-35
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; SSE: pshufd $-40
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; SSE: psubd
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; SSE: padd
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; SSE: psrld $31
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; SSE: psrad $2
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; SSE: padd
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; AVX-LABEL: test8:
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; AVX: vpmuldq
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; AVX: vpshufd $49
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; AVX: vpshufd $49
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; AVX: vpmuldq
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; AVX: vshufps $-35
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; AVX: vpshufd $-40
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; AVX: vpadd
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; AVX: vpsrld $31
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; AVX: vpsrad $2
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; AVX: vpadd
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}
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define <8 x i32> @test9(<8 x i32> %a) {
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%div = sdiv <8 x i32> %a, <i32 7, i32 7, i32 7, i32 7,i32 7, i32 7, i32 7, i32 7>
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ret <8 x i32> %div
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; AVX-LABEL: test9:
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; AVX: vpbroadcastd
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; AVX: vpalignr $4
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; AVX: vpalignr $4
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; AVX: vpmuldq
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; AVX: vpmuldq
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; AVX: vpalignr $4
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; AVX: vpblendd $170
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; AVX: vpadd
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; AVX: vpsrld $31
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; AVX: vpsrad $2
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; AVX: vpadd
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}
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define <8 x i32> @test10(<8 x i32> %a) {
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%rem = urem <8 x i32> %a, <i32 7, i32 7, i32 7, i32 7,i32 7, i32 7, i32 7, i32 7>
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ret <8 x i32> %rem
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; AVX-LABEL: test10:
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; AVX: vpbroadcastd
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; AVX: vpalignr $4
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; AVX: vpmuludq
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; AVX: vpmuludq
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; AVX: vpblendd $170
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; AVX: vpsubd
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; AVX: vpsrld $1
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; AVX: vpadd
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; AVX: vpsrld $2
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; AVX: vpmulld
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}
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define <8 x i32> @test11(<8 x i32> %a) {
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%rem = srem <8 x i32> %a, <i32 7, i32 7, i32 7, i32 7,i32 7, i32 7, i32 7, i32 7>
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ret <8 x i32> %rem
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; AVX-LABEL: test11:
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; AVX: vpbroadcastd
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; AVX: vpalignr $4
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; AVX: vpalignr $4
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; AVX: vpmuldq
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; AVX: vpmuldq
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; AVX: vpalignr $4
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; AVX: vpblendd $170
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; AVX: vpadd
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; AVX: vpsrld $31
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; AVX: vpsrad $2
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; AVX: vpadd
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; AVX: vpmulld
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}
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define <2 x i16> @test12() {
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%I8 = insertelement <2 x i16> zeroinitializer, i16 -1, i32 0
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%I9 = insertelement <2 x i16> %I8, i16 -1, i32 1
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%B9 = urem <2 x i16> %I9, %I9
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ret <2 x i16> %B9
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; AVX-LABEL: test12:
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; AVX: xorps
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}
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define <4 x i32> @PR20355(<4 x i32> %a) {
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; SSE-LABEL: PR20355:
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; SSE: movdqa {{.*}}, %[[X1:xmm[0-9]+]]
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; SSE-NEXT: movdqa %[[X1]], %[[X2:xmm[0-9]+]]
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; SSE-NEXT: psrad $31, %[[X2]]
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; SSE-NEXT: pand %xmm0, %[[X2]]
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; SSE-NEXT: movdqa %xmm0, %[[X3:xmm[0-9]+]]
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; SSE-NEXT: psrad $31, %[[X3]]
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; SSE-NEXT: pand %[[X1]], %[[X3]]
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; SSE-NEXT: paddd %[[X2]], %[[X3]]
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; SSE-NEXT: pshufd {{.*}} # [[X4:xmm[0-9]+]] = xmm0[1,0,3,0]
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; SSE-NEXT: pmuludq %[[X1]], %xmm0
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; SSE-NEXT: pshufd {{.*}} # [[X1]] = [[X1]][1,0,3,0]
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; SSE-NEXT: pmuludq %[[X4]], %[[X1]]
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; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[1,3],[[X1]][1,3]
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; SSE-NEXT: pshufd {{.*}} # [[X5:xmm[0-9]+]] = xmm0[0,2,1,3]
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; SSE-NEXT: psubd %[[X3]], %[[X5]]
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; SSE-NEXT: movdqa %[[X5]], %xmm0
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; SSE-NEXT: psrld $31, %xmm0
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; SSE-NEXT: paddd %[[X5]], %xmm0
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; SSE-NEXT: retq
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;
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; SSE41-LABEL: PR20355:
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; SSE41: movdqa {{.*}}, %[[X1:xmm[0-9]+]]
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; SSE41-NEXT: pshufd {{.*}} # [[X2:xmm[0-9]+]] = xmm0[1,0,3,0]
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; SSE41-NEXT: pmuldq %[[X1]], %xmm0
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; SSE41-NEXT: pshufd {{.*}} # [[X1]] = [[X1]][1,0,3,0]
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; SSE41-NEXT: pmuldq %[[X2]], %[[X1]]
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; SSE41-NEXT: shufps {{.*}} # xmm0 = xmm0[1,3],[[X1]][1,3]
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; SSE41-NEXT: pshufd {{.*}} # [[X3:xmm[0-9]+]] = xmm0[0,2,1,3]
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; SSE41-NEXT: movdqa %[[X3]], %xmm0
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; SSE41-NEXT: psrld $31, %xmm0
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; SSE41-NEXT: paddd %[[X3]], %xmm0
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; SSE41-NEXT: retq
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entry:
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%sdiv = sdiv <4 x i32> %a, <i32 3, i32 3, i32 3, i32 3>
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ret <4 x i32> %sdiv
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}
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