Craig Topper 6d7c1c4298 [RISCV] Don't use tail agnostic policy on instructions where destination is tied to source ... If the destination is tied, then user has some control of the register used for input. They would have the ability to control the value of any tail elements. By using tail agnostic we take this option away from them. Its not clear that the intrinsics are defined such that this isn't supposed to work. And undisturbed is a valid implementation for agnostic so code wouldn't even fail to work on all systems if we always used agnostic. The vcompress intrinsic is defined to require tail undisturbed so at minimum we need this for that instruction or need to redefine the intrinsic. I've made an exception here for vmv.s.x/fmv.s.f and reduction instructions which only write to element 0 regardless of the tail policy. This allows us to keep the agnostic policy on those which should allow better redundant vsetvli removal. An enhancement would be to check for undef input and keep the agnostic policy, but we don't have good test coverage for that yet. Reviewed By: khchen Differential Revision: https://reviews.llvm.org/D93878		2020-12-29 10:37:58 -08:00
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CMakeLists.txt	llvmbuildectomy - replace llvm-build by plain cmake	2020-11-13 10:35:24 +01:00
RISCVBaseInfo.cpp	[RISCV] Add intrinsics for vsetvli instruction	2020-12-18 12:10:09 -08:00
RISCVBaseInfo.h	[RISCV] Don't use tail agnostic policy on instructions where destination is tied to source	2020-12-29 10:37:58 -08:00
RISCVMatInt.cpp
RISCVMatInt.h