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https://github.com/RPCS3/llvm-mirror.git
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42 lines
1.8 KiB
LLVM
42 lines
1.8 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLW
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; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRW
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; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRW
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; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLH
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; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRH
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; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRH
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;
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; Make sure that the instructions with immediate operands are generated.
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; CHECK-ASLW: vaslw({{.*}}, #9)
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; CHECK-ASRW: vasrw({{.*}}, #8)
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; CHECK-LSRW: vlsrw({{.*}}, #7)
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; CHECK-ASLH: vaslh({{.*}}, #6)
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; CHECK-ASRH: vasrh({{.*}}, #5)
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; CHECK-LSRH: vlsrh({{.*}}, #4)
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target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
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target triple = "hexagon"
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define i64 @foo(i64 %x) nounwind readnone {
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entry:
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%0 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %x, i32 9)
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%1 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %x, i32 8)
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%2 = tail call i64 @llvm.hexagon.S2.lsr.i.vw(i64 %x, i32 7)
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%3 = tail call i64 @llvm.hexagon.S2.asl.i.vh(i64 %x, i32 6)
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%4 = tail call i64 @llvm.hexagon.S2.asr.i.vh(i64 %x, i32 5)
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%5 = tail call i64 @llvm.hexagon.S2.lsr.i.vh(i64 %x, i32 4)
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%add = add i64 %1, %0
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%add1 = add i64 %add, %2
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%add2 = add i64 %add1, %3
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%add3 = add i64 %add2, %4
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%add4 = add i64 %add3, %5
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ret i64 %add4
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}
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declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) nounwind readnone
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declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32) nounwind readnone
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declare i64 @llvm.hexagon.S2.lsr.i.vw(i64, i32) nounwind readnone
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declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32) nounwind readnone
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declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32) nounwind readnone
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declare i64 @llvm.hexagon.S2.lsr.i.vh(i64, i32) nounwind readnone
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