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10839866a1
This patch implements initial backend support for a -mtune CPU controlled by a "tune-cpu" function attribute. If the attribute is not present X86 will use the resolved CPU from target-cpu attribute or command line. This patch adds MC layer support a tune CPU. Each CPU now has two sets of features stored in their GenSubtargetInfo.inc tables . These features lists are passed separately to the Processor and ProcessorModel classes in tablegen. The tune list defaults to an empty list to avoid changes to non-X86. This annoyingly increases the size of static tables on all target as we now store 24 more bytes per CPU. I haven't quantified the overall impact, but I can if we're concerned. One new test is added to X86 to show a few tuning features with mismatched tune-cpu and target-cpu/target-feature attributes to demonstrate independent control. Another new test is added to demonstrate that the scheduler model follows the tune CPU. I have not added a -mtune to llc/opt or MC layer command line yet. With no attributes we'll just use the -mcpu for both. MC layer tools will always follow the normal CPU for tuning. Differential Revision: https://reviews.llvm.org/D85165
68 lines
2.2 KiB
C++
68 lines
2.2 KiB
C++
//===- NVPTXSubtarget.cpp - NVPTX Subtarget Information -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the NVPTX specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTXSubtarget.h"
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#include "NVPTXTargetMachine.h"
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using namespace llvm;
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#define DEBUG_TYPE "nvptx-subtarget"
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#define GET_SUBTARGETINFO_ENUM
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "NVPTXGenSubtargetInfo.inc"
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static cl::opt<bool>
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NoF16Math("nvptx-no-f16-math", cl::ZeroOrMore, cl::Hidden,
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cl::desc("NVPTX Specific: Disable generation of f16 math ops."),
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cl::init(false));
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// Pin the vtable to this file.
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void NVPTXSubtarget::anchor() {}
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NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
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StringRef FS) {
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// Provide the default CPU if we don't have one.
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TargetName = std::string(CPU.empty() ? "sm_20" : CPU);
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ParseSubtargetFeatures(TargetName, /*TuneCPU*/ TargetName, FS);
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// Set default to PTX 3.2 (CUDA 5.5)
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if (PTXVersion == 0) {
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PTXVersion = 32;
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}
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return *this;
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}
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NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS,
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const NVPTXTargetMachine &TM)
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: NVPTXGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), PTXVersion(0),
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SmVersion(20), TM(TM), InstrInfo(),
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TLInfo(TM, initializeSubtargetDependencies(CPU, FS)), FrameLowering() {}
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bool NVPTXSubtarget::hasImageHandles() const {
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// Enable handles for Kepler+, where CUDA supports indirect surfaces and
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// textures
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if (TM.getDrvInterface() == NVPTX::CUDA)
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return (SmVersion >= 30);
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// Disabled, otherwise
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return false;
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}
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bool NVPTXSubtarget::allowFP16Math() const {
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return hasFP16Math() && NoF16Math == false;
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}
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