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fed21911ba
Introduce basic schedule model for AMD Zen 3 CPU's, a.k.a `znver3`.
This is fully built from scratch, from llvm-mca measurements
and documented reference materials.
Nothing was copied from `znver2`/`znver1`.
I believe this is in a reasonable state of completion for inclusion,
probably better than D52779 `bdver2` was :)
Namely:
* uops are pretty spot-on (at least what llvm-mca can measure)
{F16422596}
* latency is also pretty spot-on (at least what llvm-mca can measure)
{F16422601}
* throughput is within reason
{F16422607}
I haven't run much benchmarks with this,
however RawSpeed benchmarks says this is beneficial:
{F16603978}
{F16604029}
I'll call out the obvious problems there:
* i didn't really bother with X87 instructions
* i didn't really bother with obviously-microcoded/system instructions
* There are large discrepancy in throughput for `mr` and `rm` instructions.
I'm not really sure if it's a modelling defect that needs to be fixed,
or it's a defect of measurments.
* Pipe distributions are probably bad :)
I can't do much here until AMD allows that to be fixed
by documenting the appropriate counters and updating libpfm
That being said, as @RKSimon notes:
>>! In D94395#2647381, @RKSimon wrote:
> I'll mention again that all the znver* models appear to be very inaccurate wrt SIMD/FPU instructions <...>
so how much worse this could possibly be?!
Things that aren't there:
* Various tunings: zero idioms, etc. That is follow-ups.
Differential Revision: https://reviews.llvm.org/D94395
249 lines
11 KiB
TableGen
249 lines
11 KiB
TableGen
//===-- X86PfmCounters.td - X86 Hardware Counters ----------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the available hardware counters for various subtargets.
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//
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//===----------------------------------------------------------------------===//
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def UnhaltedCoreCyclesPfmCounter : PfmCounter<"unhalted_core_cycles">;
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def UopsIssuedPfmCounter : PfmCounter<"uops_issued:any">;
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// No default counters on X86.
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def DefaultPfmCounters : ProcPfmCounters {}
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def : PfmCountersDefaultBinding<DefaultPfmCounters>;
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// Intel X86 Counters.
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def PentiumPfmCounters : ProcPfmCounters {
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let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
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let UopsCounter = PfmCounter<"uops_retired">;
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}
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def : PfmCountersBinding<"pentiumpro", PentiumPfmCounters>;
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def : PfmCountersBinding<"pentium2", PentiumPfmCounters>;
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def : PfmCountersBinding<"pentium3", PentiumPfmCounters>;
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def : PfmCountersBinding<"pentium3m", PentiumPfmCounters>;
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def : PfmCountersBinding<"pentium-m", PentiumPfmCounters>;
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def CorePfmCounters : ProcPfmCounters {
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let CycleCounter = UnhaltedCoreCyclesPfmCounter;
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let UopsCounter = PfmCounter<"uops_retired:any">;
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}
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def : PfmCountersBinding<"yonah", CorePfmCounters>;
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def : PfmCountersBinding<"prescott", CorePfmCounters>;
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def : PfmCountersBinding<"core2", CorePfmCounters>;
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def : PfmCountersBinding<"penryn", CorePfmCounters>;
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def : PfmCountersBinding<"nehalem", CorePfmCounters>;
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def : PfmCountersBinding<"corei7", CorePfmCounters>;
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def : PfmCountersBinding<"westmere", CorePfmCounters>;
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def AtomPfmCounters : ProcPfmCounters {
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let CycleCounter = UnhaltedCoreCyclesPfmCounter;
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let UopsCounter = PfmCounter<"uops_retired:any">;
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}
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def : PfmCountersBinding<"bonnell", AtomPfmCounters>;
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def : PfmCountersBinding<"atom", AtomPfmCounters>;
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def SLMPfmCounters : ProcPfmCounters {
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let CycleCounter = UnhaltedCoreCyclesPfmCounter;
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let UopsCounter = PfmCounter<"uops_retired:any">;
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}
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def : PfmCountersBinding<"silvermont", SLMPfmCounters>;
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def : PfmCountersBinding<"goldmont", SLMPfmCounters>;
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def : PfmCountersBinding<"goldmont-plus", SLMPfmCounters>;
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def : PfmCountersBinding<"tremont", SLMPfmCounters>;
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def KnightPfmCounters : ProcPfmCounters {
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let CycleCounter = UnhaltedCoreCyclesPfmCounter;
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let UopsCounter = PfmCounter<"uops_retired:all">;
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}
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def : PfmCountersBinding<"knl", KnightPfmCounters>;
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def : PfmCountersBinding<"knm", KnightPfmCounters>;
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def SandyBridgePfmCounters : ProcPfmCounters {
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let CycleCounter = UnhaltedCoreCyclesPfmCounter;
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let UopsCounter = UopsIssuedPfmCounter;
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let IssueCounters = [
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PfmIssueCounter<"SBPort0", "uops_dispatched_port:port_0">,
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PfmIssueCounter<"SBPort1", "uops_dispatched_port:port_1">,
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PfmIssueCounter<"SBPort23", "uops_dispatched_port:port_2 + uops_dispatched_port:port_3">,
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PfmIssueCounter<"SBPort4", "uops_dispatched_port:port_4">,
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PfmIssueCounter<"SBPort5", "uops_dispatched_port:port_5">
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];
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}
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def : PfmCountersBinding<"sandybridge", SandyBridgePfmCounters>;
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def : PfmCountersBinding<"ivybridge", SandyBridgePfmCounters>;
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def HaswellPfmCounters : ProcPfmCounters {
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let CycleCounter = UnhaltedCoreCyclesPfmCounter;
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let UopsCounter = UopsIssuedPfmCounter;
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let IssueCounters = [
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PfmIssueCounter<"HWPort0", "uops_executed_port:port_0">,
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PfmIssueCounter<"HWPort1", "uops_executed_port:port_1">,
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PfmIssueCounter<"HWPort2", "uops_executed_port:port_2">,
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PfmIssueCounter<"HWPort3", "uops_executed_port:port_3">,
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PfmIssueCounter<"HWPort4", "uops_executed_port:port_4">,
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PfmIssueCounter<"HWPort5", "uops_executed_port:port_5">,
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PfmIssueCounter<"HWPort6", "uops_executed_port:port_6">,
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PfmIssueCounter<"HWPort7", "uops_executed_port:port_7">
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];
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}
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def : PfmCountersBinding<"haswell", HaswellPfmCounters>;
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def BroadwellPfmCounters : ProcPfmCounters {
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let CycleCounter = UnhaltedCoreCyclesPfmCounter;
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let UopsCounter = UopsIssuedPfmCounter;
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let IssueCounters = [
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PfmIssueCounter<"BWPort0", "uops_executed_port:port_0">,
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PfmIssueCounter<"BWPort1", "uops_executed_port:port_1">,
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PfmIssueCounter<"BWPort2", "uops_executed_port:port_2">,
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PfmIssueCounter<"BWPort3", "uops_executed_port:port_3">,
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PfmIssueCounter<"BWPort4", "uops_executed_port:port_4">,
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PfmIssueCounter<"BWPort5", "uops_executed_port:port_5">,
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PfmIssueCounter<"BWPort6", "uops_executed_port:port_6">,
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PfmIssueCounter<"BWPort7", "uops_executed_port:port_7">
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];
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}
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def : PfmCountersBinding<"broadwell", BroadwellPfmCounters>;
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def SkylakeClientPfmCounters : ProcPfmCounters {
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let CycleCounter = UnhaltedCoreCyclesPfmCounter;
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let UopsCounter = UopsIssuedPfmCounter;
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let IssueCounters = [
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PfmIssueCounter<"SKLPort0", "uops_dispatched_port:port_0">,
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PfmIssueCounter<"SKLPort1", "uops_dispatched_port:port_1">,
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PfmIssueCounter<"SKLPort2", "uops_dispatched_port:port_2">,
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PfmIssueCounter<"SKLPort3", "uops_dispatched_port:port_3">,
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PfmIssueCounter<"SKLPort4", "uops_dispatched_port:port_4">,
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PfmIssueCounter<"SKLPort5", "uops_dispatched_port:port_5">,
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PfmIssueCounter<"SKLPort6", "uops_dispatched_port:port_6">,
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PfmIssueCounter<"SKLPort7", "uops_dispatched_port:port_7">
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];
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}
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def : PfmCountersBinding<"skylake", SkylakeClientPfmCounters>;
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def SkylakeServerPfmCounters : ProcPfmCounters {
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let CycleCounter = UnhaltedCoreCyclesPfmCounter;
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let UopsCounter = UopsIssuedPfmCounter;
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let IssueCounters = [
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PfmIssueCounter<"SKXPort0", "uops_dispatched_port:port_0">,
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PfmIssueCounter<"SKXPort1", "uops_dispatched_port:port_1">,
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PfmIssueCounter<"SKXPort2", "uops_dispatched_port:port_2">,
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PfmIssueCounter<"SKXPort3", "uops_dispatched_port:port_3">,
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PfmIssueCounter<"SKXPort4", "uops_dispatched_port:port_4">,
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PfmIssueCounter<"SKXPort5", "uops_dispatched_port:port_5">,
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PfmIssueCounter<"SKXPort6", "uops_dispatched_port:port_6">,
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PfmIssueCounter<"SKXPort7", "uops_dispatched_port:port_7">
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];
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}
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def : PfmCountersBinding<"skylake-avx512", SkylakeServerPfmCounters>;
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def : PfmCountersBinding<"cascadelake", SkylakeServerPfmCounters>;
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def : PfmCountersBinding<"cannonlake", SkylakeServerPfmCounters>;
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def : PfmCountersBinding<"icelake-client", SkylakeServerPfmCounters>;
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def : PfmCountersBinding<"icelake-server", SkylakeServerPfmCounters>;
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// AMD X86 Counters.
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// Set basic counters for AMD cpus that we know libpfm4 supports.
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def DefaultAMDPfmCounters : ProcPfmCounters {
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let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
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let UopsCounter = PfmCounter<"retired_uops">;
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}
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def : PfmCountersBinding<"athlon", DefaultAMDPfmCounters>;
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def : PfmCountersBinding<"athlon-tbird", DefaultAMDPfmCounters>;
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def : PfmCountersBinding<"athlon-4", DefaultAMDPfmCounters>;
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def : PfmCountersBinding<"athlon-xp", DefaultAMDPfmCounters>;
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def : PfmCountersBinding<"athlon-mp", DefaultAMDPfmCounters>;
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def : PfmCountersBinding<"k8", DefaultAMDPfmCounters>;
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def : PfmCountersBinding<"opteron", DefaultAMDPfmCounters>;
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def : PfmCountersBinding<"athlon64", DefaultAMDPfmCounters>;
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def : PfmCountersBinding<"athlon-fx", DefaultAMDPfmCounters>;
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def : PfmCountersBinding<"k8-sse3", DefaultAMDPfmCounters>;
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def : PfmCountersBinding<"opteron-sse3", DefaultAMDPfmCounters>;
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def : PfmCountersBinding<"athlon64-sse3", DefaultAMDPfmCounters>;
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def : PfmCountersBinding<"amdfam10", DefaultAMDPfmCounters>;
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def : PfmCountersBinding<"barcelona", DefaultAMDPfmCounters>;
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def BdVer2PfmCounters : ProcPfmCounters {
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let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
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let UopsCounter = PfmCounter<"retired_uops">;
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let IssueCounters = [
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PfmIssueCounter<"PdFPU0", "dispatched_fpu_ops:ops_pipe0 + dispatched_fpu_ops:ops_dual_pipe0">,
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PfmIssueCounter<"PdFPU1", "dispatched_fpu_ops:ops_pipe1 + dispatched_fpu_ops:ops_dual_pipe1">,
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PfmIssueCounter<"PdFPU2", "dispatched_fpu_ops:ops_pipe2 + dispatched_fpu_ops:ops_dual_pipe2">,
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PfmIssueCounter<"PdFPU3", "dispatched_fpu_ops:ops_pipe3 + dispatched_fpu_ops:ops_dual_pipe3">
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];
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}
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def : PfmCountersBinding<"bdver1", BdVer2PfmCounters>;
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def : PfmCountersBinding<"bdver2", BdVer2PfmCounters>;
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def BdVer3PfmCounters : ProcPfmCounters {
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let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
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let UopsCounter = PfmCounter<"retired_uops">;
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let IssueCounters = [
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PfmIssueCounter<"SrFPU0", "dispatched_fpu_ops:ops_pipe0 + dispatched_fpu_ops:ops_dual_pipe0">,
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PfmIssueCounter<"SrFPU1", "dispatched_fpu_ops:ops_pipe1 + dispatched_fpu_ops:ops_dual_pipe1">,
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PfmIssueCounter<"SrFPU2", "dispatched_fpu_ops:ops_pipe2 + dispatched_fpu_ops:ops_dual_pipe2">
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];
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}
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def : PfmCountersBinding<"bdver3", BdVer3PfmCounters>;
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def : PfmCountersBinding<"bdver4", BdVer3PfmCounters>;
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def BtVer1PfmCounters : ProcPfmCounters {
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let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
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let UopsCounter = PfmCounter<"retired_uops">;
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let IssueCounters = [
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PfmIssueCounter<"BtFPU0", "dispatched_fpu:pipe0">,
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PfmIssueCounter<"BtFPU1", "dispatched_fpu:pipe1">
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];
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}
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def : PfmCountersBinding<"btver1", BtVer1PfmCounters>;
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def BtVer2PfmCounters : ProcPfmCounters {
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let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
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let UopsCounter = PfmCounter<"retired_uops">;
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let IssueCounters = [
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PfmIssueCounter<"JFPU0", "dispatched_fpu:pipe0">,
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PfmIssueCounter<"JFPU1", "dispatched_fpu:pipe1">
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];
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}
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def : PfmCountersBinding<"btver2", BtVer2PfmCounters>;
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def ZnVer1PfmCounters : ProcPfmCounters {
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let CycleCounter = PfmCounter<"cycles_not_in_halt">;
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let UopsCounter = PfmCounter<"retired_uops">;
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let IssueCounters = [
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PfmIssueCounter<"ZnFPU0", "fpu_pipe_assignment:total0">,
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PfmIssueCounter<"ZnFPU1", "fpu_pipe_assignment:total1">,
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PfmIssueCounter<"ZnFPU2", "fpu_pipe_assignment:total2">,
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PfmIssueCounter<"ZnFPU3", "fpu_pipe_assignment:total3">,
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PfmIssueCounter<"ZnDivider", "div_op_count">
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];
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}
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def : PfmCountersBinding<"znver1", ZnVer1PfmCounters>;
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def ZnVer2PfmCounters : ProcPfmCounters {
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let CycleCounter = PfmCounter<"cycles_not_in_halt">;
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let UopsCounter = PfmCounter<"retired_uops">;
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let IssueCounters = [
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PfmIssueCounter<"Zn2AGU", "ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">,
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PfmIssueCounter<"Zn2Divider", "div_op_count">
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];
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}
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def : PfmCountersBinding<"znver2", ZnVer2PfmCounters>;
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def ZnVer3PfmCounters : ProcPfmCounters {
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let CycleCounter = PfmCounter<"cycles_not_in_halt">;
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let UopsCounter = PfmCounter<"retired_ops">;
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let IssueCounters = [
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PfmIssueCounter<"Zn3Int", "ops_type_dispatched_from_decoder:int_disp_retire_mode">,
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PfmIssueCounter<"Zn3FPU", "ops_type_dispatched_from_decoder:fp_disp_retire_mode">,
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PfmIssueCounter<"Zn3Load", "ls_dispatch:ld_dispatch">,
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PfmIssueCounter<"Zn3Store", "ls_dispatch:store_dispatch">,
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PfmIssueCounter<"Zn3Divider", "div_op_count">
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];
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}
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def : PfmCountersBinding<"znver3", ZnVer3PfmCounters>;
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