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0eee65899b
The linker or post-link optimizer can create an ELF image with multiple executable segments each of which will be loaded separately at run time. This breaks the assumption of llvm-profgen that currently only supports one base load address. What it ends up with is that the subsequent mmap events will be treated as an overwrite of the first mmap event which will in turn screw up address mapping. While it is non-trivial to support multiple separate load addresses and given that on x64 those segments will always be loaded at consecutive addresses (though via separate mmap sys calls), I'm adding an error checking logic to bail out if that's violated and keep using a single load address which is the address of the first executable segment. Also changing the disassembly output from printing section offset to printing the virtual address instead, which matches the behavior of objdump. Differential Revision: https://reviews.llvm.org/D103178
41 lines
3.1 KiB
Plaintext
41 lines
3.1 KiB
Plaintext
; REQUIRES: x86-registered-target
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; RUN: llvm-profgen --binary=%S/Inputs/symbolize.perfbin --perfscript=%s --output=%t1 --show-disassembly-only -x86-asm-syntax=intel --show-source-locations | FileCheck %s --match-full-lines
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; RUN: llvm-profgen --binary=%S/Inputs/symbolize.perfbin --perfscript=%s --output=%t2 --show-disassembly-only -x86-asm-syntax=intel --show-source-locations --show-canonical-fname | FileCheck %s --match-full-lines --check-prefix=CHECK-CANO
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; CHECK: Disassembly of section .text [0x520, 0x62c]:
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; CHECK: <funcA.llvm.1000>:
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; CHECK-NEXT: 5e0: mov eax, edi funcA.llvm.1000:0
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; CHECK-NEXT: 5e2: mov edx, dword ptr [rip + 2099768] funcLeaf:2 @ funcA.llvm.1000:1
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; CHECK-NEXT: 5e8: mov ecx, edx fib:2 @ funcLeaf:2 @ funcA.llvm.1000:1
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; CHECK-NEXT: 5ea: add ecx, 3 fib:2 @ funcLeaf:2 @ funcA.llvm.1000:1
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; CHECK-NEXT: 5ed: cmp edx, 3 fib:2 @ funcLeaf:2 @ funcA.llvm.1000:1
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; CHECK-NEXT: 5f0: cmovl ecx, edx fib:2 @ funcLeaf:2 @ funcA.llvm.1000:1
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; CHECK-NEXT: 5f3: sub eax, ecx funcLeaf:2 @ funcA.llvm.1000:1
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; CHECK-NEXT: 5f5: ret funcA.llvm.1000:2
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; CHECK-CANO: <funcA>:
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; CHECK-CANO-NEXT: 5e0: mov eax, edi funcA:0
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; CHECK-CANO-NEXT: 5e2: mov edx, dword ptr [rip + 2099768] funcLeaf:2 @ funcA:1
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; CHECK-CANO-NEXT: 5e8: mov ecx, edx fib:2 @ funcLeaf:2 @ funcA:1
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; CHECK-CANO-NEXT: 5ea: add ecx, 3 fib:2 @ funcLeaf:2 @ funcA:1
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; CHECK-CANO-NEXT: 5ed: cmp edx, 3 fib:2 @ funcLeaf:2 @ funcA:1
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; CHECK-CANO-NEXT: 5f0: cmovl ecx, edx fib:2 @ funcLeaf:2 @ funcA:1
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; CHECK-CANO-NEXT: 5f3: sub eax, ecx funcLeaf:2 @ funcA:1
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; CHECK-CANO-NEXT: 5f5: ret funcA:2
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; CHECK: <funcLeaf>:
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; CHECK-NEXT: 600: mov eax, edi funcLeaf:1
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; CHECK-NEXT: 602: mov edx, dword ptr [rip + 2099736] funcLeaf:2
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; CHECK-NEXT: 608: mov ecx, edx fib:2 @ funcLeaf:2
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; CHECK-NEXT: 60a: add ecx, 3 fib:2 @ funcLeaf:2
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; CHECK-NEXT: 60d: cmp edx, 3 fib:2 @ funcLeaf:2
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; CHECK-NEXT: 610: cmovl ecx, edx fib:2 @ funcLeaf:2
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; CHECK-NEXT: 613: sub eax, ecx funcLeaf:2
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; CHECK-NEXT: 615: ret funcLeaf:3
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; CHECK: <fib>:
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; CHECK-NEXT: 620: mov eax, edi fib:2
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; CHECK-NEXT: 622: add eax, 3 fib:2
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; CHECK-NEXT: 625: cmp edi, 3 fib:2
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; CHECK-NEXT: 628: cmovl eax, edi fib:2
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; CHECK-NEXT: 62b: ret fib:8
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; symbolize.perfbin is from the following compile commands:
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; clang %S/Inputs/symbolize.ll -shared -fPIC -o %S/Inputs/symbolize.perfbin |