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https://github.com/RPCS3/llvm-mirror.git
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b5fa754985
The code here seems to date back to r134705, when tablegen lowering was first being added. I don't believe that we need to include CPSR implicit operands on the MCInst. This now works more like other backends (like AArch64), where all implicit registers are skipped. This allows the AliasInst for CSEL's to match correctly, as can be seen in the test changes. Differential revision: https://reviews.llvm.org/D66703 llvm-svn: 370745
341 lines
8.7 KiB
LLVM
341 lines
8.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi %s -verify-machineinstrs -o - | FileCheck %s
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define i32 @csinc_const_65(i32 %a) {
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; CHECK-LABEL: csinc_const_65:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r1, #5
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: cinc r0, r1, gt
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 45
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%spec.select = select i1 %cmp, i32 6, i32 5
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ret i32 %spec.select
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}
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define i32 @csinc_const_56(i32 %a) {
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; CHECK-LABEL: csinc_const_56:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r1, #5
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: cinc r0, r1, le
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 45
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%spec.select = select i1 %cmp, i32 5, i32 6
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ret i32 %spec.select
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}
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define i32 @csinc_const_zext(i32 %a) {
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; CHECK-LABEL: csinc_const_zext:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: cset r0, gt
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 45
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%spec.select = zext i1 %cmp to i32
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ret i32 %spec.select
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}
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define i32 @csinv_const_56(i32 %a) {
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; CHECK-LABEL: csinv_const_56:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r1, #5
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: cinv r0, r1, gt
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 45
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%spec.select = select i1 %cmp, i32 -6, i32 5
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ret i32 %spec.select
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}
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define i32 @csinv_const_65(i32 %a) {
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; CHECK-LABEL: csinv_const_65:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r1, #5
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: cinv r0, r1, le
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 45
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%spec.select = select i1 %cmp, i32 5, i32 -6
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ret i32 %spec.select
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}
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define i32 @csinv_const_sext(i32 %a) {
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; CHECK-LABEL: csinv_const_sext:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: csetm r0, gt
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 45
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%spec.select = sext i1 %cmp to i32
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ret i32 %spec.select
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}
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define i32 @csneg_const(i32 %a) {
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; CHECK-LABEL: csneg_const:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r1, #1
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: cneg r0, r1, le
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 45
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%spec.select = select i1 %cmp, i32 1, i32 -1
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ret i32 %spec.select
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}
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define i32 @csneg_const_r(i32 %a) {
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; CHECK-LABEL: csneg_const_r:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r1, #1
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: cneg r0, r1, gt
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 45
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%spec.select = select i1 %cmp, i32 -1, i32 1
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ret i32 %spec.select
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}
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define i32 @csel_var(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: csel_var:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: it le
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; CHECK-NEXT: movle r1, r2
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 45
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%spec.select = select i1 %cmp, i32 %b, i32 %c
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ret i32 %spec.select
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}
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define i32 @csinc_var(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: csinc_var:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: csinc r0, r1, r2, gt
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 45
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%cplus1 = add nsw i32 %c, 1
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%spec.select = select i1 %cmp, i32 %b, i32 %cplus1
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ret i32 %spec.select
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}
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define i32 @csinc_swap_var(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: csinc_swap_var:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: csinc r0, r2, r1, le
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 45
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%bplus1 = add nsw i32 %b, 1
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%spec.select = select i1 %cmp, i32 %bplus1, i32 %c
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ret i32 %spec.select
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}
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define i32 @csinv_var(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: csinv_var:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: csinv r0, r1, r2, gt
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 45
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%cinv = xor i32 %c, -1
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%spec.select = select i1 %cmp, i32 %b, i32 %cinv
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ret i32 %spec.select
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}
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define i32 @csinv_swap_var(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: csinv_swap_var:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: csinv r0, r2, r1, le
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 45
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%binv = xor i32 %b, -1
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%spec.select = select i1 %cmp, i32 %binv, i32 %c
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ret i32 %spec.select
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}
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define i32 @csneg_var(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: csneg_var:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: csneg r0, r1, r2, gt
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 45
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%cneg = sub i32 0, %c
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%spec.select = select i1 %cmp, i32 %b, i32 %cneg
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ret i32 %spec.select
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}
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define i32 @csneg_swap_var_sgt(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: csneg_swap_var_sgt:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: csneg r0, r2, r1, le
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 45
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%bneg = sub i32 0, %b
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%spec.select = select i1 %cmp, i32 %bneg, i32 %c
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ret i32 %spec.select
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}
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define i32 @csneg_swap_var_sge(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: csneg_swap_var_sge:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #44
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; CHECK-NEXT: csneg r0, r2, r1, le
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sge i32 %a, 45
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%bneg = sub i32 0, %b
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%spec.select = select i1 %cmp, i32 %bneg, i32 %c
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ret i32 %spec.select
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}
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define i32 @csneg_swap_var_sle(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: csneg_swap_var_sle:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #46
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; CHECK-NEXT: csneg r0, r2, r1, ge
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sle i32 %a, 45
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%bneg = sub i32 0, %b
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%spec.select = select i1 %cmp, i32 %bneg, i32 %c
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ret i32 %spec.select
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}
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define i32 @csneg_swap_var_slt(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: csneg_swap_var_slt:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: csneg r0, r2, r1, ge
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp slt i32 %a, 45
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%bneg = sub i32 0, %b
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%spec.select = select i1 %cmp, i32 %bneg, i32 %c
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ret i32 %spec.select
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}
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define i32 @csneg_swap_var_ugt(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: csneg_swap_var_ugt:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: csneg r0, r2, r1, ls
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp ugt i32 %a, 45
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%bneg = sub i32 0, %b
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%spec.select = select i1 %cmp, i32 %bneg, i32 %c
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ret i32 %spec.select
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}
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define i32 @csneg_swap_var_uge(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: csneg_swap_var_uge:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #44
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; CHECK-NEXT: csneg r0, r2, r1, ls
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp uge i32 %a, 45
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%bneg = sub i32 0, %b
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%spec.select = select i1 %cmp, i32 %bneg, i32 %c
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ret i32 %spec.select
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}
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define i32 @csneg_swap_var_ule(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: csneg_swap_var_ule:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #46
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; CHECK-NEXT: csneg r0, r2, r1, hs
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp ule i32 %a, 45
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%bneg = sub i32 0, %b
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%spec.select = select i1 %cmp, i32 %bneg, i32 %c
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ret i32 %spec.select
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}
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define i32 @csneg_swap_var_ult(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: csneg_swap_var_ult:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: csneg r0, r2, r1, hs
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp ult i32 %a, 45
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%bneg = sub i32 0, %b
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%spec.select = select i1 %cmp, i32 %bneg, i32 %c
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ret i32 %spec.select
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}
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define i32 @csneg_swap_var_ne(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: csneg_swap_var_ne:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: csneg r0, r2, r1, ne
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp eq i32 %a, 45
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%bneg = sub i32 0, %b
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%spec.select = select i1 %cmp, i32 %bneg, i32 %c
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ret i32 %spec.select
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}
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define i32 @csneg_swap_var_eq(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: csneg_swap_var_eq:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r0, #45
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; CHECK-NEXT: csneg r0, r2, r1, eq
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp ne i32 %a, 45
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%bneg = sub i32 0, %b
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%spec.select = select i1 %cmp, i32 %bneg, i32 %c
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ret i32 %spec.select
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}
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define i32 @csinc_inplace(i32 %a, i32 %b) {
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; CHECK-LABEL: csinc_inplace:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r1, #45
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; CHECK-NEXT: cinc r0, r0, gt
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %b, 45
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%inc = zext i1 %cmp to i32
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%spec.select = add nsw i32 %inc, %a
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ret i32 %spec.select
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}
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define i32 @csinv_inplace(i32 %a, i32 %b) {
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; CHECK-LABEL: csinv_inplace:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r1, #45
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; CHECK-NEXT: cinv r0, r0, gt
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %b, 45
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%sub = sext i1 %cmp to i32
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%xor = xor i32 %sub, %a
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ret i32 %xor
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}
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