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Summary: First, we need to explain the core of the vulnerability. Note that this is a very incomplete description, please see the Project Zero blog post for details: https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html The basis for branch target injection is to direct speculative execution of the processor to some "gadget" of executable code by poisoning the prediction of indirect branches with the address of that gadget. The gadget in turn contains an operation that provides a side channel for reading data. Most commonly, this will look like a load of secret data followed by a branch on the loaded value and then a load of some predictable cache line. The attacker then uses timing of the processors cache to determine which direction the branch took *in the speculative execution*, and in turn what one bit of the loaded value was. Due to the nature of these timing side channels and the branch predictor on Intel processors, this allows an attacker to leak data only accessible to a privileged domain (like the kernel) back into an unprivileged domain. The goal is simple: avoid generating code which contains an indirect branch that could have its prediction poisoned by an attacker. In many cases, the compiler can simply use directed conditional branches and a small search tree. LLVM already has support for lowering switches in this way and the first step of this patch is to disable jump-table lowering of switches and introduce a pass to rewrite explicit indirectbr sequences into a switch over integers. However, there is no fully general alternative to indirect calls. We introduce a new construct we call a "retpoline" to implement indirect calls in a non-speculatable way. It can be thought of loosely as a trampoline for indirect calls which uses the RET instruction on x86. Further, we arrange for a specific call->ret sequence which ensures the processor predicts the return to go to a controlled, known location. The retpoline then "smashes" the return address pushed onto the stack by the call with the desired target of the original indirect call. The result is a predicted return to the next instruction after a call (which can be used to trap speculative execution within an infinite loop) and an actual indirect branch to an arbitrary address. On 64-bit x86 ABIs, this is especially easily done in the compiler by using a guaranteed scratch register to pass the target into this device. For 32-bit ABIs there isn't a guaranteed scratch register and so several different retpoline variants are introduced to use a scratch register if one is available in the calling convention and to otherwise use direct stack push/pop sequences to pass the target address. This "retpoline" mitigation is fully described in the following blog post: https://support.google.com/faqs/answer/7625886 We also support a target feature that disables emission of the retpoline thunk by the compiler to allow for custom thunks if users want them. These are particularly useful in environments like kernels that routinely do hot-patching on boot and want to hot-patch their thunk to different code sequences. They can write this custom thunk and use `-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this case, on x86-64 thu thunk names must be: ``` __llvm_external_retpoline_r11 ``` or on 32-bit: ``` __llvm_external_retpoline_eax __llvm_external_retpoline_ecx __llvm_external_retpoline_edx __llvm_external_retpoline_push ``` And the target of the retpoline is passed in the named register, or in the case of the `push` suffix on the top of the stack via a `pushl` instruction. There is one other important source of indirect branches in x86 ELF binaries: the PLT. These patches also include support for LLD to generate PLT entries that perform a retpoline-style indirection. The only other indirect branches remaining that we are aware of are from precompiled runtimes (such as crt0.o and similar). The ones we have found are not really attackable, and so we have not focused on them here, but eventually these runtimes should also be replicated for retpoline-ed configurations for completeness. For kernels or other freestanding or fully static executables, the compiler switch `-mretpoline` is sufficient to fully mitigate this particular attack. For dynamic executables, you must compile *all* libraries with `-mretpoline` and additionally link the dynamic executable and all shared libraries with LLD and pass `-z retpolineplt` (or use similar functionality from some other linker). We strongly recommend also using `-z now` as non-lazy binding allows the retpoline-mitigated PLT to be substantially smaller. When manually apply similar transformations to `-mretpoline` to the Linux kernel we observed very small performance hits to applications running typical workloads, and relatively minor hits (approximately 2%) even for extremely syscall-heavy applications. This is largely due to the small number of indirect branches that occur in performance sensitive paths of the kernel. When using these patches on statically linked applications, especially C++ applications, you should expect to see a much more dramatic performance hit. For microbenchmarks that are switch, indirect-, or virtual-call heavy we have seen overheads ranging from 10% to 50%. However, real-world workloads exhibit substantially lower performance impact. Notably, techniques such as PGO and ThinLTO dramatically reduce the impact of hot indirect calls (by speculatively promoting them to direct calls) and allow optimized search trees to be used to lower switches. If you need to deploy these techniques in C++ applications, we *strongly* recommend that you ensure all hot call targets are statically linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well tuned servers using all of these techniques saw 5% - 10% overhead from the use of retpoline. We will add detailed documentation covering these components in subsequent patches, but wanted to make the core functionality available as soon as possible. Happy for more code review, but we'd really like to get these patches landed and backported ASAP for obvious reasons. We're planning to backport this to both 6.0 and 5.0 release streams and get a 5.0 release with just this cherry picked ASAP for distros and vendors. This patch is the work of a number of people over the past month: Eric, Reid, Rui, and myself. I'm mailing it out as a single commit due to the time sensitive nature of landing this and the need to backport it. Huge thanks to everyone who helped out here, and everyone at Intel who helped out in discussions about how to craft this. Also, credit goes to Paul Turner (at Google, but not an LLVM contributor) for much of the underlying retpoline design. Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D41723 llvm-svn: 323155
122 lines
4.6 KiB
C++
122 lines
4.6 KiB
C++
//===-- X86.h - Top-level interface for X86 representation ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the x86
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// target library, as used by the LLVM JIT.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86_H
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#define LLVM_LIB_TARGET_X86_X86_H
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#include "llvm/Support/CodeGen.h"
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namespace llvm {
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class FunctionPass;
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class ImmutablePass;
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class InstructionSelector;
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class ModulePass;
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class PassRegistry;
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class X86RegisterBankInfo;
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class X86Subtarget;
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class X86TargetMachine;
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/// This pass converts a legalized DAG into a X86-specific DAG, ready for
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/// instruction scheduling.
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FunctionPass *createX86ISelDag(X86TargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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/// This pass initializes a global base register for PIC on x86-32.
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FunctionPass *createX86GlobalBaseRegPass();
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/// This pass combines multiple accesses to local-dynamic TLS variables so that
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/// the TLS base address for the module is only fetched once per execution path
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/// through the function.
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FunctionPass *createCleanupLocalDynamicTLSPass();
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/// This function returns a pass which converts floating-point register
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/// references and pseudo instructions into floating-point stack references and
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/// physical instructions.
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FunctionPass *createX86FloatingPointStackifierPass();
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/// This pass inserts AVX vzeroupper instructions before each call to avoid
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/// transition penalty between functions encoded with AVX and SSE.
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FunctionPass *createX86IssueVZeroUpperPass();
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/// This pass inserts ENDBR instructions before indirect jump/call
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/// destinations as part of CET IBT mechanism.
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FunctionPass *createX86IndirectBranchTrackingPass();
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/// Return a pass that pads short functions with NOOPs.
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/// This will prevent a stall when returning on the Atom.
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FunctionPass *createX86PadShortFunctions();
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/// Return a pass that selectively replaces certain instructions (like add,
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/// sub, inc, dec, some shifts, and some multiplies) by equivalent LEA
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/// instructions, in order to eliminate execution delays in some processors.
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FunctionPass *createX86FixupLEAs();
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/// Return a pass that removes redundant LEA instructions and redundant address
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/// recalculations.
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FunctionPass *createX86OptimizeLEAs();
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/// Return a pass that transforms setcc + movzx pairs into xor + setcc.
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FunctionPass *createX86FixupSetCC();
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/// Return a pass that expands WinAlloca pseudo-instructions.
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FunctionPass *createX86WinAllocaExpander();
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/// Return a pass that optimizes the code-size of x86 call sequences. This is
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/// done by replacing esp-relative movs with pushes.
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FunctionPass *createX86CallFrameOptimization();
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/// Return an IR pass that inserts EH registration stack objects and explicit
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/// EH state updates. This pass must run after EH preparation, which does
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/// Windows-specific but architecture-neutral preparation.
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FunctionPass *createX86WinEHStatePass();
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/// Return a Machine IR pass that expands X86-specific pseudo
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/// instructions into a sequence of actual instructions. This pass
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/// must run after prologue/epilogue insertion and before lowering
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/// the MachineInstr to MC.
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FunctionPass *createX86ExpandPseudoPass();
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/// This pass converts X86 cmov instructions into branch when profitable.
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FunctionPass *createX86CmovConverterPass();
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/// Return a Machine IR pass that selectively replaces
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/// certain byte and word instructions by equivalent 32 bit instructions,
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/// in order to eliminate partial register usage, false dependences on
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/// the upper portions of registers, and to save code size.
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FunctionPass *createX86FixupBWInsts();
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/// Return a Machine IR pass that reassigns instruction chains from one domain
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/// to another, when profitable.
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FunctionPass *createX86DomainReassignmentPass();
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void initializeFixupBWInstPassPass(PassRegistry &);
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/// This pass replaces EVEX encoded of AVX-512 instructiosn by VEX
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/// encoding when possible in order to reduce code size.
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FunctionPass *createX86EvexToVexInsts();
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/// This pass creates the thunks for the retpoline feature.
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ModulePass *createX86RetpolineThunksPass();
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InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
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X86Subtarget &,
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X86RegisterBankInfo &);
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void initializeEvexToVexInstPassPass(PassRegistry &);
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} // End llvm namespace
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#endif
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