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46d19bc0c7
If the arch is P8, we will select XFLOAD to load the floating point, and then, expand it to vsx and non-vsx X-form instruction post RA. This patch is trying to convert the X-form to D-form if it meets the requirement that one operand of the x-form inst is the special Zero register, and another operand fed by add inst. i.e. y = add imm, reg LFDX. 0, y --> LFD imm(reg) Reviewers: Nemanjai Differential Revision: https://reviews.llvm.org/D49007 llvm-svn: 340149
122 lines
4.5 KiB
LLVM
122 lines
4.5 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PPC64-P8
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PPC64
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PPC64-P8
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PPC64
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; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32
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define i128 @test_abs(ppc_fp128 %x) nounwind {
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entry:
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; PPC64-LABEL: test_abs:
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; PPC64-DAG: stfd 2, [[OFFSET_HI:-?[0-9]+]]([[SP:[0-9]+]])
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; PPC64-DAG: stfd 1, [[OFFSET_LO:-?[0-9]+]]([[SP]])
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; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
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; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]])
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; PPC64-DAG: rldicr [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0
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; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
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; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]]
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; PPC64: blr
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; PPC64-P8-LABEL: test_abs:
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; PPC64-P8-DAG: mffprd [[LO:[0-9]+]], 2
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; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1
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; PPC64-P8-DAG: rldicr [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0
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; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
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; PPC64-P8-DAG: xor 4, [[LO]], [[FLIP_BIT]]
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; PPC64-P8: blr
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; PPC32-DAG: stfd 1, 24(1)
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; PPC32-DAG: stfd 2, 16(1)
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; PPC32-DAG: lwz [[HI0:[0-9]+]], 24(1)
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; PPC32-DAG: lwz [[LO0:[0-9]+]], 16(1)
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; PPC32-DAG: lwz [[HI1:[0-9]+]], 28(1)
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; PPC32-DAG: lwz [[LO1:[0-9]+]], 20(1)
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; PPC32: rlwinm [[FLIP_BIT:[0-9]+]], [[HI0]], 0, 0, 0
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; PPC32-DAG: xor [[HI0]], [[HI0]], [[FLIP_BIT]]
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; PPC32-DAG: xor [[LO0]], [[LO0]], [[FLIP_BIT]]
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; PPC32: blr
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%0 = tail call ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128 %x)
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%1 = bitcast ppc_fp128 %0 to i128
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ret i128 %1
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}
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define i128 @test_neg(ppc_fp128 %x) nounwind {
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entry:
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; PPC64-LABEL: test_neg:
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; PPC64-DAG: stfd 2, [[OFFSET_HI:-?[0-9]+]]([[SP:[0-9]+]])
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; PPC64-DAG: stfd 1, [[OFFSET_LO:-?[0-9]+]]([[SP]])
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; PPC64-DAG: li [[FLIP_BIT:[0-9]+]], 1
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; PPC64-DAG: sldi [[FLIP_BIT]], [[FLIP_BIT]], 63
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; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
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; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]])
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; PPC64-NOT: BARRIER
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; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
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; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]]
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; PPC64: blr
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; PPC64-P8-LABEL: test_neg:
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; PPC64-P8-DAG: mffprd [[LO:[0-9]+]], 2
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; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1
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; PPC64-P8-DAG: li [[IMM1:[0-9]+]], 1
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; PPC64-P8-DAG: sldi [[FLIP_BIT:[0-9]+]], [[IMM1]], 63
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; PPC64-P8-NOT: BARRIER
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; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
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; PPC64-P8-DAG: xor 4, [[LO]], [[FLIP_BIT]]
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; PPC64-P8: blr
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; PPC32-DAG: stfd 1, 24(1)
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; PPC32-DAG: stfd 2, 16(1)
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; PPC32-DAG: lwz [[HI0:[0-9]+]], 24(1)
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; PPC32-DAG: lwz [[LO0:[0-9]+]], 16(1)
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; PPC32-DAG: lwz [[HI1:[0-9]+]], 28(1)
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; PPC32-DAG: lwz [[LO1:[0-9]+]], 20(1)
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; PPC32-NOT: BARRIER
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; PPC32-DAG: xoris [[HI0]], [[HI0]], 32768
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; PPC32-DAG: xoris [[LO0]], [[LO0]], 32768
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; PPC32: blr
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%0 = fsub ppc_fp128 0xM80000000000000000000000000000000, %x
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%1 = bitcast ppc_fp128 %0 to i128
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ret i128 %1
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}
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define i128 @test_copysign(ppc_fp128 %x) nounwind {
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entry:
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; PPC64-LABEL: test_copysign:
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; PPC64-DAG: stfd 1, [[OFFSET:-?[0-9]+]](1)
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; PPC64-DAG: li [[HI_TMP:[0-9]+]], 16399
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; PPC64-DAG: li [[LO_TMP:[0-9]+]], 3019
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; PPC64-NOT: BARRIER
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; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
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; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
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; PPC64-DAG: ld [[X_HI:[0-9]+]], [[OFFSET]](1)
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; PPC64-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0
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; PPC64-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
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; PPC64-DAG: xor 4, [[NEW_HI_TMP]], [[CST_LO]]
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; PPC64: blr
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; PPC64-P8-LABEL: test_copysign:
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; PPC64-P8-DAG: mffprd [[X_HI:[0-9]+]], 1
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; PPC64-P8-DAG: li [[HI_TMP:[0-9]+]], 16399
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; PPC64-P8-DAG: li [[LO_TMP:[0-9]+]], 3019
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; PPC64-P8-NOT: BARRIER
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; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
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; PPC64-P8-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
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; PPC64-P8-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0
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; PPC64-P8-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
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; PPC64-P8-DAG: xor 4, [[NEW_HI_TMP]], [[CST_LO]]
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; PPC64-P8: blr
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; PPC32: stfd 1, [[STACK:[0-9]+]](1)
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; PPC32: lwz [[HI:[0-9]+]], [[STACK]](1)
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; PPC32: rlwinm [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0, 0
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; PPC32-NOT: BARRIER
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; PPC32-DAG: oris {{[0-9]+}}, [[FLIP_BIT]], 16399
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; PPC32-DAG: xoris {{[0-9]+}}, [[FLIP_BIT]], 48304
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; PPC32: blr
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%0 = tail call ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128 0xM400F000000000000BCB0000000000000, ppc_fp128 %x)
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%1 = bitcast ppc_fp128 %0 to i128
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ret i128 %1
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}
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declare ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128)
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declare ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128, ppc_fp128)
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