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d29969d956
This patch aims to improve the codegen for vector loads involving the scalar_to_vector (load X) sequence. Initially, ld->mv instructions were used for scalar_to_vector (load X), so this patch allows scalar_to_vector (load X) to utilize: LXSD and LXSDX for i64 and f64 LXSIWAX for i32 (sign extension to i64) LXSIWZX for i32 and f64 Committing on behalf of Amy Kwan. Differential Revision: https://reviews.llvm.org/D48950 llvm-svn: 339260
28 lines
1.2 KiB
LLVM
28 lines
1.2 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck --check-prefix=CHECK-LE \
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; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck \
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; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s
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define <16 x i8> @test(i32* %s, i32* %t) {
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; CHECK-LE-LABEL: test:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: lfiwzx f0, 0, r3
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; CHECK-LE-NEXT: xxpermdi vs0, f0, f0, 2
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; CHECK-LE-NEXT: xxspltw v2, vs0, 3
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; CHECK-LE-NEXT: blr
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lfiwzx f0, 0, r3
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; CHECK-NEXT: xxsldwi vs0, f0, f0, 1
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; CHECK-NEXT: xxspltw v2, vs0, 0
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; CHECK-NEXT: blr
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entry:
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%0 = bitcast i32* %s to <4 x i8>*
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%1 = load <4 x i8>, <4 x i8>* %0, align 4
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%2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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ret <16 x i8> %2
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}
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