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e23fa40f7f
An encoding does not allow to use SDWA in an instruction with scalar operands, either literals or SGPRs. That is however possible to copy these operands into a VGPR first. Several copies of the value are produced if multiple SDWA conversions were done. To cleanup MachineLICM (to hoist copies out of loops), MachineCSE (to remove duplicate copies) and SIFoldOperands (to replace SGPR to VGPR copy with immediate copy right to the VGPR) runs are added after the SDWA pass. Differential Revision: https://reviews.llvm.org/D33583 llvm-svn: 304219
37 lines
1.4 KiB
LLVM
37 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; If the workgroup id range is restricted, we should be able to use
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; mad24 for the usual indexing pattern.
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declare i32 @llvm.amdgcn.workgroup.id.x() #0
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0
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; GCN-LABEL: {{^}}get_global_id_0:
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; GCN: s_and_b32 [[WGSIZEX:s[0-9]+]], {{s[0-9]+}}, 0xffff
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; GCN: v_mov_b32_e32 [[VWGSIZEX:v[0-9]+]], [[WGSIZEX]]
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; GCN: v_mad_u32_u24 v{{[0-9]+}}, s8, [[VWGSIZEX]], v0
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define amdgpu_kernel void @get_global_id_0(i32 addrspace(1)* %out) #1 {
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%dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
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%cast.dispatch.ptr = bitcast i8 addrspace(2)* %dispatch.ptr to i32 addrspace(2)*
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%gep = getelementptr inbounds i32, i32 addrspace(2)* %cast.dispatch.ptr, i64 1
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%workgroup.size.xy = load i32, i32 addrspace(2)* %gep, align 4, !invariant.load !0
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%workgroup.size.x = and i32 %workgroup.size.xy, 65535
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%workitem.id.x = call i32 @llvm.amdgcn.workitem.id.x(), !range !1
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%workgroup.id.x = call i32 @llvm.amdgcn.workgroup.id.x(), !range !2
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%mul = mul i32 %workgroup.id.x, %workgroup.size.x
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%add = add i32 %mul, %workitem.id.x
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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!0 = !{}
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!1 = !{i32 0, i32 1024}
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!2 = !{i32 0, i32 16777216}
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