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d5cead992a
This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
17 lines
730 B
LLVM
17 lines
730 B
LLVM
; RUN: llc -o - %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after expand-isel-pseudos | FileCheck %s
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; This test verifies that the instruction selection will add the implicit
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; register operands in the correct order when modifying the opcode of an
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; instruction to V_ADD_I32_e32.
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; CHECK: %{{[0-9]+}}:vgpr_32 = V_ADD_I32_e32 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def %vcc, implicit %exec
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define amdgpu_kernel void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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entry:
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%b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
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%a = load volatile i32, i32 addrspace(1)* %in
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%b = load volatile i32, i32 addrspace(1)* %b_ptr
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%result = add i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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