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854153de5a
The VSX versions have the advantage of a full 64-register target whereas the FP ones have the advantage of lower latency and higher throughput. So what we’re after is using the faster instructions in low register pressure situations and using the larger register file in high register pressure situations. The heuristic chooses between the following 7 pairs of instructions. PPC::LXSSPX vs PPC::LFSX PPC::LXSDX vs PPC::LFDX PPC::STXSSPX vs PPC::STFSX PPC::STXSDX vs PPC::STFDX PPC::LXSIWAX vs PPC::LFIWAX PPC::LXSIWZX vs PPC::LFIWZX PPC::STXSIWX vs PPC::STFIWX Differential Revision: https://reviews.llvm.org/D38486 llvm-svn: 318651
62 lines
2.2 KiB
LLVM
62 lines
2.2 KiB
LLVM
; Verify that small structures and float arguments are passed in the
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; least significant part of a stack slot doubleword.
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; RUN: llc -verify-machineinstrs < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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%struct.large_arg = type { [8 x i64] }
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%struct.small_arg = type { i16, i8 }
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@gl = common global %struct.large_arg zeroinitializer, align 8
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@gs = common global %struct.small_arg zeroinitializer, align 2
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@gf = common global float 0.000000e+00, align 4
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define void @callee1(%struct.small_arg* noalias nocapture sret %agg.result, %struct.large_arg* byval nocapture readnone %pad, %struct.small_arg* byval nocapture readonly %x) {
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entry:
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%0 = bitcast %struct.small_arg* %x to i32*
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%1 = bitcast %struct.small_arg* %agg.result to i32*
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%2 = load i32, i32* %0, align 2
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store i32 %2, i32* %1, align 2
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ret void
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}
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; CHECK: @callee1
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; CHECK: lwz {{[0-9]+}}, 104(1)
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; CHECK: blr
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define void @caller1() {
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entry:
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%tmp = alloca %struct.small_arg, align 2
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call void @test1(%struct.small_arg* sret %tmp, %struct.large_arg* byval @gl, %struct.small_arg* byval @gs)
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ret void
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}
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; CHECK: @caller1
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; CHECK: stw {{[0-9]+}}, 104(1)
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; CHECK: bl test1
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declare void @test1(%struct.small_arg* sret, %struct.large_arg* byval, %struct.small_arg* byval)
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define float @callee2(float %pad1, float %pad2, float %pad3, float %pad4, float %pad5, float %pad6, float %pad7, float %pad8, float %pad9, float %pad10, float %pad11, float %pad12, float %pad13, float %x) {
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entry:
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ret float %x
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}
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; CHECK: @callee2
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; CHECK: addi [[TOCREG:[0-9]+]], 1, 136
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; CHECK: lfsx {{[0-9]+}}, {{[0-9]+}}, [[TOCREG]]
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; CHECK: blr
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define void @caller2() {
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entry:
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%0 = load float, float* @gf, align 4
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%call = tail call float @test2(float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float %0)
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ret void
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}
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; CHECK: @caller2
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; CHECK: addi [[TOCOFF:[0-9]+]], {{[0-9]+}}, 136
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; CHECK: stfsx {{[0-9]+}}, 0, [[TOCOFF]]
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; CHECK: bl test2
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declare float @test2(float, float, float, float, float, float, float, float, float, float, float, float, float, float)
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